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White Paper: “How to test high-speed memory with non-intrusive embedded instruments”

24th July 2012

ES Admin

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Whitepaper

A new white paper from ASSET InterTech explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others.

Several studies by the International Electronics Manufacturing Initiative have shown that testing memory and memory buses on circuit boards is one of the most pressing problems for system manufacturers.

Access for legacy probe-based testers through test pads on circuit boards is disappearing because the capacitive coupling effects caused by a test pad will disrupt the signaling on the memory bus. Consequently, manufacturers are turning to non-intrusive software-based test methods which are more cost-effective and provide observed data straight from the receiver.

The white paper describes the engineering tradeoffs involved with several non-intrusive test methods, including processor-controlled test, FPGA-controlled test, memory built-in self test, boundary-scan test and functional test.

The 21-page paper is written by Al Crouch, ASSET’s chief technologist for core instrumentation and vice-chairman of the working group developing the IEEE P1687 Internal JTAG standard for embedded instruments.