Uniquify Delivers High-Performance DDR3 Memory System Running in Low-Cost, Wire Bond Package

The DDR3 IP subsystem is implemented in a customer design in a low-power 28-nanometer (nm) process for a high-volume consumer application that requires the use of a low-cost wire bond package.

Uniquify was able to achieve 2100Mbps (1.05Ghz clock rate) performance in the selected wire bond package favored by price-sensitive consumer electronics product manufacturers as an alternative to higher cost flip chip packages. This performance was made possible through application of Uniquify’s adaptive technologies, dynamic self-calibrating logic (DSCL) and dynamic adaptive bit calibration (DABC).

“This unheard of DDR3 performance in wire bond packaging is a testament to the power of our patented dynamic adaptive DDR technologies, DSCL and DABC,” says Sam Kim, chief operating officer of Uniquify. “Using our adaptive DDR IP, design teams will be able to deliver higher performance products while enjoying the lower cost benefits of wire bond packaging. In short, this is a game-changer for a cost sensitive market like consumer electronics!”

The performance boost is due to Uniquify’s patented and adaptive DSCL and DABC technologies built into its DDR PHY IP. DSCL dynamically tracks the DDR timing and automatically centers the sample point in the middle of the window, allowing the DDR clock speed to be increased without sacrificing stability or requiring the use of a more expensive package. DABC performs dynamic skew alignment at the bit level that further improves the quality of the DDR timing. The ability to achieve the highest performance with low system cost is a result of employing DSCL and DABC in the on-chip DDR IP subsystem.