SRAM devices suppress soft error occurrences

The SRAMs achieve the same soft error rate as earlier devices fabricated in a 150nm process. Suitable for data storage in battery-backup devices, the SRAM devices achieve low-power operation, with a standby current of maximum of 2µA at 25°C.

Alongside increased performance and functionality, reliability is critical in user systems. Therefore, SRAM devices need to be particularly reliable, providing measures to deal with soft errors due to alpha rays and neutrons in cosmic radiation. To provide resistance against soft errors, the memory nodes of the SRAMs feature a capacitor. Traditionally, soft errors are dealt with by SRAM devices or user systems via an ECC circuit, which corrects the errors. However, the effectiveness of this technique is dependent on the performance of the ECC. For example, some ECCs may not be able to correct multiple bit errors. Renesas has, therefore, adopted structural measures that suppress soft error occurrence itself.

Additionally, the load transistors (p-channel) in the SRAM cell are formed as polysilicon TFT devices, and as they are stacked in the upper layer of the n-channel MOS transistors that are formed on the silicon substrate, only n-channel transistors are formed on the underlying silicon substrate.

According to the company, the design of the SRAM devices makes them more reliable than full CMOS type devices that have the ordinary memory cell structure. The reliability in which the SRAMs provide makes them suitable for FA equipment, test equipment, smart grid related equipment and transportation systems.

By combining polysilicon TFT stacking technology with stacked transistor technology, the SRAM devices achieve a compact cell size. To illustrate: the cell size in Renesas 110nm Advanced LP SRAMs is comparable to that in a full CMOS type SRAMs fabricated in a 65nm process.