SoC memory improvements highlighted at IEDM 2017

Another breakthrough was a high-density SRAM bitcell on Leti’s CoolCube 3D platform, which reduces the area required for memory by 30%, while maintaining full device functionality. This breakthrough points the way to easing the major memory bottleneck in more complex systems on chip (SoC), where up to 90% of the SoC area might be taken by SRAM.

The breakthroughs were reported 5th December at IEDM 2017 in a paper titled Advanced Memory Solutions for Emerging Circuits and Systems.

A key obstacle to shrinking SRAM on SoCs is bitcell-area limitations linked to required performance and yield, both of which become more challenging as technology scales. Lowering system power consumption is also limited by memory, as the SRAM performance and its stability scale less successfully than logic performance at lower voltages. Other memories like CAM might be affected even more by voltage scaling.

“All of these obstacles become particularly important for the Internet of Things, where ultralow-power consumption and the cost of individual nodes are crucial, and SRAM limitations have a big impact on both,” said Bastien Giraud, one of the paper authors.

Leti approached these challenges with a CoolCube SRAM design focusing on the development of a compact and functional four-transistor bitcell, along with other innovations:

• Reconfiguring memory between the CAM and SRAM, depending on the application
• Optimising memory using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, Flip Flops (FF) and refresh-free Dynamic Random Access Memory (DRAM) 
• A new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays

Leti said its proposed CAM/SRAM outperforms state-of-the-art memories, with operations at 1.56GHz and 0.13fJ/bit energy per search. In addition, the proposed TFET designs are competitive in terms of area, performance and static power consumption. Leti’s proposed compensation technique in crosspoint memory also enables the design of cost-efficient large memory arrays, while reducing the impact of temporal and spatial variations.

Short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability. “In the longer term, Leti’s CoolCube technology will be able to deliver very high-density SRAM,” Giraud said. “Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.”