Renesas announce 4MB advanced low-power SRAM devices

The forthcoming SRAMs are the new series of Advanced LPSRAM and provide high reliability equivalent to that of Renesas’ existing SRAM products adopting a 150 nm process, including soft error free and latch-up free. They also achieve low-power operation with a standby current of maximum of 2 microamperes at 25°C, making them suitable for data storage in battery-backup devices.

Renesas’ low-power SRAMs have achieved widespread adoption in many different fields, including industrial, office, communication, automotive, and consumer products and the company held the No. 1 market share worldwide in such products in 2012. Recently, as manufacturers systems have attained higher performance and more advanced functionality, SRAM has become an important factor in improving overall system reliability. In particular, SRAM used to store important information such as system programs and billing data must provide a high level of reliability, and particular attention has come to be focused on measures to reduce soft error caused by alpha radiation and cosmic neutron radiation.

Renesas’ Advanced LP SRAM has structure in which each memory node within the memory cells hast an added physical capacitor, resulting in extremely high endurance against soft error. A general method of dealing with soft error after they occur is the inclusion of an internal error correcting code circuit in the SRAM or the manufacturer systems. This approach has its limits, however, and there may be cases where the performance of the ECC is unable to deal with errors affecting multiple bits. In contrast, Advanced LP SRAMs use structural measures to prevent the soft error themselves from occurring. Results from the evaluation of system soft error in 150 nm Advanced LP SRAMs that are currently in mass production prove that, in practical terms, these products can be called soft error free.

In addition, the SRAM cell load transistors (P-channels) are polysilicon TFTs and they are stacked on top of the N-channel MOS transistors on the silicon substrate. Therefore, only the N-channel transistors are formed below on the silicon substrate. This ensures that no parasitic thyristors can form within the memory area and theoretically makes latchups impossible.

These features enable Advanced LP SRAMs to achieve far higher levels of reliability than full CMOS-type products using a conventional memory cell structure. Advanced LP SRAMs can contribute to even better performance and reliability in applications where a high level of reliability is essential, such as factory automation equipment, measuring devices, equipment employed in smart grids, and transportation systems.

Furthermore, Advanced LP SRAM combines SRAM polysilicon TFT stacking technology and stacked capacitor technology to reduce the cell size. For example, the cell size of 110 nm Advanced LP SRAM is comparable to that of full CMOS SRAM fabricated using a 65 nm process.

Renesas intends to strengthen its lineup of 110 nm SRAMs by adding 8 Mb and 64 Mb 110 nm products.