Reduce data centre memory power consumption by 60%

Renesas' reference design enables 100Gb traffic packet header search functionality using 1/15th the number of memory devices than would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60%.

With the arrival of the IoT era and the rapid increase in the volume of data flowing to and from connected devices, increasing network speeds has become a priority. In particular, more data centres are switching their traffic speeds from 40 to 100Gb to support the increasing volume of data, and the increasing number of search entries. However, boosting the speed of network equipment typically brings an increase in power consumption, and this raises issues such as device package temperature and power costs. Also, widespread adoption of SDN and NFV brings the need for frequent modification of the network configuration by software and creates demand for network equipment supporting flexible reconfiguration. Against this background, Renesas has developed a power-efficient packet header search reference design able to process high-speed traffic. It incorporates an FPGA, allowing flexible network configuration and LLDRAM-III memory capable of storing one million or more search entries.

LLDRAM-III is a power-efficient type of low-latency memory from Renesas that supports 400 mega accesses (read or write operations) per second and consumes 2W or less to transfer 57.6Gb of data. By combining this memory with the newly-developed search algorithm from Renesas, it is possible to process 150 million packet header searches per second, as required for 100Gb Ethernet, using a single LLDRAM-III device. Performing the same processing with a configuration using a conventional search algorithm and standard DRAM would require around 15 memory devices and consume about 5W of power. The new reference design reduces the number of memory devices to a single LLDRAM-III memory  and cuts memory power consumption by 60%. This shrinks the memory mounting area by 90% and also reduces the number of signal lines between the memory and FPGA by 90%, making it possible to configure the system using an FPGA with fewer pins and contributing to reduced overall cost.

The exact-match search IP allows the flexibility of changing the search key length in one-bit units up to a maximum of 143 bits. This makes it possible to accommodate not only conventional MAC address searches but also new communication protocols made possible by advances in network virtualisation technology without having to modify the search IP design. Also, the number of search entries can be expanded to two million or even four million by specifying a shorter maximum search key length. This also includes functionality that supports simultaneous output of search results and packet processing rules when the maximum search key length of 143 bits is used, by dividing the search key area and the packet processing rule area appended to the search result.

The development support tools consist of:

• A reference board with proven interoperability between the FPGA and LLDRAM-III, thereby saving time that would otherwise be needed for design and verification;
• Sample design including search IP;
• A complete verification environment; and
• A complete evaluation environment.

These tools enable users to begin FPGA subsystem design and network equipment design work in parallel, which significantly reduces the development cycle time by around six months (according to calculations by Renesas).

Renesas provides NSEs for the complex communication processing at the 200Gb class used by external communication interfaces of data centres and backbone communication networks. For communication processing at 100Gb and below, in applications within data centres having large numbers of ports, Renesas provides a packet header search reference design composed of LLDRAM-III and FPGA. With this new FPGA-based search solution that enables flexible communication and support for rapidly-advancing network technology, Renesas continues its commitment to the communications market with the development of new solutions.