Making memories

As we reach the physical limits of silicon devices, memory remains a key area for potential innovation. It typically takes-up large amounts of SoC die area, and consumes significant amounts of energy. Manufacturers of IoT devices are pushing for denser, faster and more energy efficient memory, but there is still a gap between what’s required and what existing techniques can actually do. A number of interesting memory technologies have emerged to try to fill this gap, some of which are quite novel. Here’s a closer look at some of the most recent developments.

3D XPoint for low latency

Attracting a lot of attention in the industry is the Intel/Micron joint venture, IMFT, and its 3D XPoint memory. This technology is said to be a thousand times faster than NAND Flash (95,000 I/O operations per second with 9ms latency) along with much greater endurance, which isn’t based on the number of read and write cycles the memory incurs. The exact nature of 3D XPoint memory is still top secret, however, we do know that it is made-up of memory cells connected by word and bit lines, with each memory cell at a cross point. Individual cells are then addressed via the word and bit lines. These structures can be stacked on top of each other in huge arrays, making it a very dense solution - crucially, there are no transistors attached to the cells, meaning it can be easily scaled to smaller dimensions.

Intel and Micron claim that the speed advantage is down to a combination of not having to block erase and then rewrite, having fast access to the cells via the metal word and bit lines, and the cell switching time, which is said to be very low. All we know about the cells so far is that they operate using a property of their material, using a fundamentally different technique to traditional NAND, which stores electrons in a floating gate structure. The exact switching mechanism is still a mystery, though there is some speculation in the industry that 3D XPoint may be a form of phase change memory. Phase change memory uses chalcogenide glass cells, which are heated to change them between crystalline (low resistance) and amorphous (high resistance) phases. 3D XPoint is expected to enter mass production in 12-18 months.

Copper ion movement

Another interesting non-volatile memory technology has come out of Adesto, which uses a technique called conductive bridging RAM (CBRAM) to make an extremely low power non-volatile memory.

CBRAM inserts additional metallisation and dielectric layers between CMOS interconnect metal layers which form the memory cells, on top of standard CMOS transistor structures. When voltages and currents are applied, electrochemical deposition or dissolution of copper occurs between the layers, forming or breaking an electrically conductive link between the layers. This link changes the cell’s resistance significantly, which is used to represent a 1 or 0. Crucially, this happens very quickly - switching time is less than a microsecond, compared to a millisecond for standard Flash, and each cell doesn’t need pre-erasing. The result is a robust non-volatile memory that writes 20 times faster than Flash, while consuming 10 to 100 times less energy.

Given the low power nature of its technology, Adesto is primarily targeting IoT battery operated and energy harvesting devices with its CBRAM. Their latest product family, Moneta, has been designed to use 50 to 100 times less power than standard Flash - it comes in 32, 64, 128 and 256kB options.

Memory plus analogue chips

Renesas has also been working on its memory technology - it’s developed a 90nm one-transistor MONOS (metal oxide nitride oxide silicon) Flash memory technology for automotive control systems. This memory technology is the first in the industry to achieve over 100 million program/erase cycles at high junction temperature (Tj of 175°C) with low rewrite energy consumption of 0.07mJ/8KB.

The interesting thing is Renesas’ new MONOS Flash memory which is compatible with the CMOS and BiCDMOS (bipolar CMOS DMOS) process technologies that automotive analogue and power chips commonly use. Combining Flash memory on analogue and power chips means an external EEPROM isn’t required, so the number of devices in automotive motor control systems can be reduced.

Although MONOS Flash isn’t a new technology itself (Renesas has been using it on MCUs for more than 20 years), the combination of outstanding program/erase endurance and low power consumption is certainly a breakthrough. Part of it is down to a new ASPC (adaptable slope pulse control) technology which allows smoother signal pulses to be used when rewriting, helping to boost endurance. ASPC also monitors the current when pulses are applied so the clock frequency can be switched to its optimum value automatically - this helps reduce current and therefore power consumption.

Gamma radiation resistant

A memory technology that’s resistant to the gamma radiation used in medical sterilisation has been developed at Maxim Integrated. Gamma radiation is commonly used on medical equipment, but it is not compatible with traditional floating gate memory technology because gamma’s high ionising radiation would erase the memory. Use cases for this new memory include single use, disposable medical sensors - the memory typically changes state when the sensor is used, preventing it from being re-used, even after sterilisation. Alternatively, manufacturers can program the embedded memory of a medical device prior to sending it for sterilisation before use.

Maxim’s memory technology is resistant to gamma radiation up to 75kGy (25 to 50kGy is typically used in sterilisation). It doesn’t use floating gate memory - a proprietary non-reversible oxide state change technique is used instead, which isn’t sensitive to gamma radiation. New layout techniques have also been used to protect any vulnerable areas of the circuit.

Maxim’s new memory comes in the form of the DS28E80, a 248-byte non-volatile EEPROM. It is organised as 8-byte blocks, and each memory block can be rewritten eight times. The DS28E80 communicates via Maxim’s 1-Wire bus, which minimises the interface to a single contact to save space.

Lower power SRAM

SureCore, the Sheffield company working on low power SRAM IP, entered the market last year. The company has come up with a way to vastly reduce the power consumption of FD-SOI (fully depleted silicon on insulator) SRAM, typically reducing dynamic power by 50% or more and static power by 35% compared to typical solutions, though there is a ten percent area penalty. The target applications for this optimised memory include battery powered wearable devices and IoT end nodes where power consumption is crucial.

Typical methods of reducing power consumption for SRAM rely on DVFS (dynamic voltage and frequency scaling). Since the power consumed by memory cells is proportional to frequency and the square of the voltage, these variables can be controlled on the fly for different parts of the memory in order to optimise power consumption. However, since SRAM needs to stay powered up to retain data, there is a limit to how much the voltage can be reduced, especially as process geometries shrink. What SureCore has done is optimise its SRAM for power consumption by reducing the number of long high swing signals, controlling the bitline voltage swing (even in the presence of high process variability) and prioritising the inputs to cones of logic to minimise the number of active gates.

Recent advances for SureCore include a new compiler for FD-SOI (full depleted silicon on insulator) 28nm memory, which supports the company’s low power, single port SRAM IP and dual port SRAM IP for FD-SOI, offering capacities up to 1Mbit with word lengths up to 288 bits. Next on the roadmap is a 40nm ultra-low power FDSOI SRAM compiler, and 40nm and 28nm Bulk CMOS ultra-low power and low power SRAM solutions.