KIOXIA and Sandisk unveil 3D Flash MemoryTechnology

Leveraging this high-speed technology, the companies expect the new 3D flash memory to achieve a 33% improvement in NAND interface speed compared with their 8th generation 3D flash memory currently in mass production, reaching a 4.8Gb/s interface speed. The technology can also deliver enhanced power efficiency of data input/output, reducing power consumption by 10% for input and 34% for output, thereby achieving a balance of high performance and low power consumption. Previewing the 10th generation 3D flash memory, the companies detailed that by increasing the number of memory layers to 332 and optimising the floor plan for increased planar density, the technology improves bit density by 59%.

“Next to the demand for increased power efficiency in data centres, data generation is set to vastly increase, driven by new AI technology-driven applications, with sophisticated operations such as inference at the Edge and the application of transfer learning techniques further compounding storage requirements.” reflects Axel Stoermann, Vice President and Chief Technology Officer, KIOXIA Europe GmbH. “KIOXIA continues to lay the groundwork supporting these storage requirements of the future: higher speeds, larger capacity, and lower power consumption.”

SVP of Global Strategy and Technology at Sandisk, Alper Ilkbahar, said: "As AI advances, customer needs for memory are becoming increasingly diverse. Through our CBA technology innovation, we aim to launch products that deliver the best mix in terms of capacity, speed, performance, and capital efficiency to cater to our customers across market segments."

KIOXIA and Sandisk also shared plans for the upcoming 9th generation 3D flash memory. Enabled by their CBA technology, the companies can combine the new CMOS technology with an existing memory cell technology to deliver capital-efficient, high-performance, low-power products. Both companies remain committed to developing cutting-edge flash memory technologies, offering tailored solutions to meet customer needs, and contributing to the advancement of the digital society.

1: Technology wherein each CMOS wafer and cell array wafer are manufactured separately in their optimised condition and then bonded together.

2: Technology wherein the bus for command/address input and the bus for data transfer are completely separated into different buses and are used in parallel. This reduces data input/output time.

3: Technology wherein power sources for existing 1.2V and additional lower voltage are utilised for the NAND interface power source. This reduces power consumption during data input/output.

*1Gbps is calculated as 1,000,000,000bits/second. This value is obtained under specific our test environment, and may vary depending on use conditions.

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