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Integrated logic and 12Mbit memory chip replaces FPGAs and RAM for video buffering

8th June 2006

Staff Reporter

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DT Electronics has introduced the Logic Devices LF3312 frame buffer / FIFO. The new device simplifies the design of digital video and data buffering systems by replacing both standard synchronous Random Access Memories (RAM) and Field Programmable Gate Array (FPGA) logic with a single chip. The LF3312 is the most flexible memory device for buffering multiple video formats. It uses both sequential and random access addressing and integrates both high-density 12Mbit memory and advanced addressing control logic.

The device features up to four data ports. Flexible addressing allows it to perform First-In First-Out (FIFO), Shift Register, Synchronization, and mixed Sequential/Random Access functions. With just over 12.4Mbits of memory and a maximum data rate of 74MHz, the LF3312 can buffer multiple video formats, including HDTV. Devices can be cascaded to enable larger word-widths or FIFO depths. A seamless address space is maintained in the Random Access mode, even when cascading multiple devices for high-resolution images. Memory can be allocated as a single 12.4Mbit FIFO memory, or as two independently controlled 6Mbit FIFO memories. Two independent memories enable multi-channel applications, such as buffering Luma and Chroma video components or multi-channel synchronization. The Input/Output word widths are configurable to 8, 10, 12, 16, 20 or 24bits without wasting memory.
The LF3312 is aimed at broadcast video equipment, medical imaging, video editing systems, security surveillance systems, and machine vision.

The LF3312 is packaged in a 15mm x 15mm small form factor 172-pin Low Profile Ball Grid Array (LBGA) package. The packages are available in RoHS compliant Green (Pb-free and beyond) packaging.