Memory
Hardware latencies associated with PRU-initiated memory reads
The PRU is a scalar processor, processing each instruction sequentially. With the exception of memory read instructions, all PRU instructions execute in a single cycle. However, the execution time of PRU read instructions varies based on memory access latencies.
Subsequent instructions will not execute until the completion of the read instruction and may impact time-sensitive operations and applications.
To learn more, click here.
Featured products
MAX17793
Analog Devices Inc.
3V to 80V, 3A, High-Efficiency, Synchronous Step-Down DC-DC Converter
| SKU: | MAX17793 |
|---|---|
| Stock: | 9316 |
| Cost: | $3.64 |
MAX22516
Analog Devices Inc.
IO-Link Data Link Controller with Transceiver and Integrated DC-DC
| SKU: | MAX22516 |
|---|---|
| Stock: | 8000 |
| Cost: | $5.42 |
