Flash memory and how to prepare for memory sourcing challenges

This article originally appeared in the July'22 magazine issue of Electronic Specifier Design – see ES's Magazine Archives for more featured publications.

Why have the shortages occurred?

With COVID restrictions designed to limit contact between people, many manufacturing businesses were forced to close temporarily. At the same time, demand for big-ticket items such as private and commercial vehicles dropped as consumers considered their economic uncertainty. Industries impacted by these changes cancelled orders for semiconductor products. Simultaneously, with everyone learning and working from home, demand for consumer products, such as tablets, monitors, and laptops, shot up.

Semiconductor vendors filled their manufacturing capacity with these new orders to stem this demand. Then, as lockdown restrictions eased, a perfect storm occurred as cancelled orders were resubmitted to factories already operating at capacity. Complex semiconductor devices typically take several months to manufacture, so wafer starts won’t happen unless there is enough orders forecast for a product. Currently, the industry is struggling to prioritise manufacturing to satisfy as many customers as possible, but there are still many buyers who are missing out.

Such problems have led to purchasing teams and design engineers coming together to assess appropriate mitigation strategies. Some highly specialised semiconductor devices, such as microcontrollers and advanced analogue solutions, are complicated to swap out. However, flash memories, with their standardised pinouts and interfaces, seem, on paper at least, to be a less-challenging exchange. But, as always, the challenges lie in the details and, if a second-source device was not approved during the development process, it is unlikely that a simple device swap will suffice. Even if an alternate flash memory functions first time round, there may be hidden issues that could cause premature failures in the field due to high[1]er-than-expected wear.

SLC NAND

SLC NAND flash, available with both serial and parallel interfaces, provides a relatively good level of compatibility between suppliers. At the physical level, pin placement and packages should be the same, although the solderability and suitability of the reels for pick-and-place equipment should still be checked. At the hardware interface level, Serial NAND uses SPI (the Serial Peripheral Interface). Due to the various ways the interface can be implemented in microcontroller units and system-on-chips, a basic test setup should be constructed to ensure that the flash memory can be accessed. The same applies for parallel NAND flash, where the timing of signals may need to be tuned using registers internal to the MCU or SoC.

This leads to the next challenge: the software. If the application code has followed best practices with the low-level drivers handling the interface and the higher levels handling the specifics of the external memory device and file system, any changes to the code should be reasonably straightforward. Adjustments may involve adding support for additional registers or changing the code to support an entirely different register implementation. Devices such as KIOXIA’s Serial Interface NAND have hardware error correction code (ECC) support that can be enabled or disabled.

The default setting of ‘enabled’, or the precise method to disengage ECC, may not match that of the device being replaced. Devices such as KIOXIA’s BENAND have integrated ECC capable of eight bits of error correction and nine bits of error detection. However, parallel SLC NAND in KIOXIA’s latest 24nm technology node relies on the host processor to generate an 8-bit ECC for each 512-byte block of memory.

When 5 or 6 erroneous bits are found, the firmware is responsible for rewriting the block in its entirety. This process, of course, increases the wear on the memory even though no write was executed at the application level in the software. The engineering team will need to closely compare the datasheets of their original flash memory choice with the replacement solution to understand how these additional memory writes will impact the lifetime of the flash storage.

Thanks to the higher level of standardisation in the world of managed flash devices, switching suppliers for e-MMC and UFS (Universal Flash Storage) storage is slightly more straightforward. The JEDEC standard JESD84-B51A version 5.1a defines the features and electrical interface of e-MCC. Released in 2019, it is generally not thought that further changes will be made, lowering the likelihood of physical interoperability issues between SoCs and storage.

e-MMC devices provide separate write/erase cycle registers for their ‘Enhanced’ (pSLC) and ‘Normal’ (MLC/TLC) blocks. However, such ‘health status’ registers only increment in steps of 10%, which is not very granular.

Additionally, this information only provides guidance on memory health. Reading ‘100% worn’ from this register does not mean that the flash doesn’t work: just like how the low profile of a car tyre doesn’t indicate an accident will happen, it merely states that a disaster around the corner is more likely.

UFS is newer, with the JEDEC standard JESD220E (also known as version 3.1) released back in early 2020. Thanks to its significantly higher throughput, it has rapidly established itself as the preferred storage option in smartphones and is gaining market share in automotive. With developers keen to obtain more status information from their storage to optimise the user experience, it is expected that this standard will continue to be updated to support these needs.

While an initial physical exchange of flash storage medium may be successful, it is necessary to understand how the internal controller manages data. While the application may only execute a certain quantity of data writes, the flash controller may instigate additional block erases and page writes as it attempts to reorganise unused dead space. This disparity between application writes by the host SoC and the writes actually written to the raw flash cells is known as the write amplification factor (WAF). A perfect WAF would be one, but a good target value for a typical application is four.

The precise way that host writes translate into flash cell writes is flash storage supplier dependent. So, while the workload may have already been assessed during the sourcing of the original flash storage solution, the analysis process will need to be repeated with the supplier of the chosen new device.

Get support and get it early

Because of the high level of compatibility at pin and package level and standardisation or similarity in interfacing for flash storage, it is easy to assume that sourcing an alternative device will be simple. However, the reality is far different. Standardisation definitely simplifies the process, but subtle hardware differences must be understood and are not always visible in the device datasheets.

Should sourcing issues be seen on the horizon, it is highly recommended to engage directly with flash suppliers and to discuss your needs quickly. Engineering teams will be able to analyse workload traces and provide guidance on any changes required when switching storage device suppliers. Additionally, commercial teams can offer advice on delivery timeframes. With the months-long manufacturing times for flash storage, they will be grateful for the insight into your demand – vital to ensure that you get the products you want when you need them.