Uniquify Extends Patented Timing Calibration Innovation to Solve Dynamic Variation in DDR Memory Subsystems

It allows the memory subsystem timing calibration to be applied during system operation, critical to enhancing system yield and maintaining DDR memory system performance as temperature and supply voltages fluctuate during system operation. The new variation-aware DSCL technology is included with Uniquify’s high-performance DDR PHY/Controller subsystem IP.

“DSCL is an important addition as even small changes in system operating parameters over time can degrade memory performance and cause failures,” remarks Josh Lee, Uniquify's founder and chief executive officer. “This will become an even greater issue as the industry adopts next-generation DDR4 memories with stringent timing requirements.

Today’s deep sub-micron SoC designs integrate DDR memory subsystems that operate at multi-gigahertz (GHz) clock rates, resulting in read-write timing margins measured in picoseconds. Designing the DDR memory subsystem to accommodate variations in system-level timing parameters during read and write cycles is challenging. Satisfying these critical timing requirements can require exhaustive rounds of incremental system-level parameter tuning, yet the resulting silicon often fails to deliver optimal system yield in volume production.

Uniquify's initial SCL technology solves this problem by performing an automatic self-calibration at system power-up for optimal DDR interface timing. DDR memory subsystems implemented with SCL exhibit higher yield due to their ability to automatically adapt critical timing characteristics for a wide range of system-level design choices and for variations in both the SoC and DDR memory processes.
The new DSCL technology builds on SCL by extending the precise timing calibration to execute dynamically during system operation, not just at system power on. During system operation, temperature and supply voltages vary over time, degrading DDR memory performance and, if severe enough, can cause intermittent memory subsystem failure.

DSCL automatically re-calibrates the critical DDR memory interface timing at user-specified intervals during system operation. It is typically set to operate during periods of lower activity for the smallest impact on system throughput. The DSCL calibration is fast and the hardware required to support the addition of DSCL is minimal.

“We integrated Uniquify’s DDR memory controller subsystem with the SCL capability into a successful video processing ASIC I was in charge of at Nethra Imaging,” says Dr. Ramana Rao, currently director of engineering at Applied Micro. “SCL enabled us to automate the calibration of the DDR interface. This was more efficient than the typical, manual process of byte-lane alignment on the interface. The addition of the industry-first dynamic SCL capability will definitely provide system-level yield improvement since automatic re-calibration will make the system more robust against changes in conditions over time.”

Adds Uniquify’s Josh Lee: We are pleased to see the fast rate of adoption of our SCL and DSCL technology. We believe that variation-aware IP will be a critical element in enabling the continued growth of the IP business. By improving device and system yield and by shortening new system bring-up time, design teams will be able to experience better margins and faster time to market.”

Availability
Licensed to electronics companies worldwide, Uniquify's SCL and DSCL technologies now are included in all of its DDR memory controller IP offerings, including DDR1, DDR2, DDR3, DDR2/3, LPDDR1 and LPDDR2 phy and controller IP.