Memory
64-layer 3D flash memory features stacked cell structure
Toshiba unveiled today the latest generation of its BiCS FLASH 3D flash memory with a stacked cell structure, a 64-layer device that will be first in the world to start sample shipments today. The new device incorporates 3-bit-per-cell (Triple-Level Cell, TLC) technology and achieves a 256Gb (32GB) capacity, an advance that underscores the potential of Toshiba’s proprietary architecture.
World’s First UFS removable memory card line-up
Samsung Electronics unveiled the industry’s first removable memory cards based on the JEDEC UFS 1.0 Card Extension Standard, for use in high-resolution mobile shooting devices such as DSLRs, 3D VR cameras, action cams and drones. Coming in a wide range of storage capacities including 256, 128, 64 and 32 GB, Samsung’s UFS cards are expected to bring a significant performance boost to the external memory storage market, allowing much mo...
Reduce data centre memory power consumption by 60%
Renesas Electronics has announced a packet header search reference design for 100Gb communications devices such as routers, switches and servers. The reference design is comprised of: the LLDRAM-III (RMHE41A364AGBG) power-efficient, LLDRAM; proprietary exact-match search IP and LLDRAM-III controller IP on an FPGA device; and development support tools.
Rambus to acquire Memory Interconnect Business from Inphi
Rambus has announced it has signed a definitive agreement to purchase the Memory Interconnect Business from Inphi for $90m. The acquisition includes all assets of the Inphi Memory Interconnect Business including product inventory, customer contracts, supply chain agreements and intellectual property.
Memory cards target cost-sensitive applications
The F-50 series is an extension to Swissbit’s existing F-60/F-600 CFast 2.0 card portfolio. It is available at Rutronix. This new series delivers up to 500/330MB/s read/write performance for cost sensitive applications. The new F-50 products complement the high performance, high endurance durabit F-60 devices by offering a DRAM-less product for cost sensitive applications with use cases that don’t require the extreme IOPS rate and end...
256M CMOS SDRAMs are offered in 86-Pin TSOP II packages
Alliance Memory has extended its offering of 256M high-speed CMOS synchronous DRAMs (SDRAM) with two x32 devices in the 86-pin, 400mm, plastic TSOP II package. Internally configured as four banks of 8M word x 32 bits, the high-density AS4C8M32S-6TIN and AS4C8M32S-7TCN provide reliable drop-in, pin-for-pin-compatible replacements for a number of similar solutions in industrial, commercial, medical and networking products requiring high memory band...
Server solutions for hyperscale data centres
A reference design that supports the burgeoning workloads of the hyperscale data centre; Integrated Device Technology (IDT) announces its collaboration with Cavium. The IDT DDR4 memory interface solutions are incorporated into the reference design, which is built on Cavium's ThunderX family of workload-optimized 64-bit ARMv8-based processors.
Sub-nanosecond operation of nonvolatile memory
The research group of Professor Hideo Ohno and Associate Professor Shunsuke Fukami of Tohoku University has demonstrated the sub-nanosecond operation of a nonvolatile magnetic memory device. Recently, the concept of IoT - a giant network of connected devices, people and things - has been attracting a great deal of attention.
How the memristor works at an atomic scale
In experiments at two Department of Energy national labs – SLAC and Lawrence Berkeley – scientists at HPE have experimentally confirmed critical aspects of how a new type of microelectronic device, the memristor, works at an atomic scale. This result is an important step in designing these solid-state devices for use in future computer memories that operate much faster, last longer and use less energy than today's flash memory. T...
sureCore delivers 40nmULP memory compiler
sureCore Ltd., the low power SRAM IP leader, has announced the immediate availability of its TSMC 40nmULP process technology memory compiler. The new compiler facilitates utilisation of sureCore's recently announced 40nm Ultra Low Voltage SRAM IP that effectively operates at a record-setting 0.6V across process voltage and temperature.