Power, performance and security: the new requirements for IoT device controllers

However, the IoT (the idea of connecting a device, even something as simple as a room thermostat or a luminaire, to the internet) is still in its infancy. Independent forecasts by analysts and semiconductor industry organisations, however, suggest that the IoT market (for end products) will have doubled in the period 2016-2019, and that some 30 billion devices will be connected to the internet by 2020.

Since the build-out of the IoT is still in an early phase, OEM development teams have, to date, generally been using pre-IoT microcontrollers in their IoT device designs. Yet the constraints of operating in the IoT environment place new demands on a device’s host controller - demands that these legacy controllers were never designed to satisfy.

Because of this, IoT device designers now have in many cases a choice to make - whether to modify existing designs based on an older controller, bolting on the additional features and capabilities required to support internet connectivity and cloud-based applications; or whether to start afresh with one of a new generation of controllers designed specifically for the requirements of IoT devices.

This article describes those new requirements, and the ways in which they can be satisfied in a single microcontroller-like system-on-chip.

The four crucial attributes of an IoT controller
There are of course many different models for connecting devices on the edge of the internet to the cloud, and for deriving the maximum value at the device level from a connection to the internet.

Nevertheless, a few new requirements are clearly shared across many classes of IoT devices. They are:

• Low power: Many new IoT devices are battery powered. Here, designers are looking to maximise run-time between charges while minimising the size and cost of the battery. Even in mains-powered devices, high power efficiency tends to aid thermal management, and enables the designer to minimise the size and cost of components such as heat sinks.
• High processing capability: In many cases, the purpose of internet connectivity is to generate and use data, so IoT devices tend to be equipped with multiple sensors and input devices. Users also increasingly demand smartphone-like user interfaces, with graphical displays and touch sensing controls. These features call for considerable processing power – a requirement that is normally, of course, in opposition to the requirement for low power operation.
• Security: When operating on the world’s universal network, IoT devices must protect the privacy of users, protect themselves from interference, verify their identity and protect data from being accessed or modified without authorisation. The security requirements of an IoT device are therefore far greater than those typically built into equivalent unconnected devices.
• Connectivity: Wired interfaces such as USB and Ethernet are commonly found in legacy microcontrollers and processors, but many new IoT devices require a wireless connection. Here the standard Bluetooth Low Energy (BLE) and WiFi technologies have emerged as the preferred choice because they are supported by an installed base of billions of smartphones and tablets.

This combination of requirements exceeds the capabilities of legacy, pre-IoT microcontrollers and processors. Legacy devices have tended to be optimised for either low power or high performance - not both. Security capabilities are also limited - IoT device designers are therefore required to integrate discrete security components, such as authentication ICs and cryptographic processors, into their designs alongside the controller. And connectivity typically also requires additional, discrete components. This means that the designer is faced with the drawbacks of a high component count and large board footprint while having to accept an unwanted trade-off of power against performance.

It should be said that these legacy controller products are not bad controllers. It is just that requirements have changed, and they are not ideally suited to the new requirements. Now a new microcontroller family built from the ground up for the IoT environment shows that the drawbacks of these legacy parts can be avoided.

Building on a programmable architecture
This new architecture is the PSoC 6 MCU from Cypress Semiconductor. The PSoC 6 is based on the same programmable building blocks as other members of the PSoC family - these are software defined digital and analogue peripherals which the user may configure, normally in the PSoC Creator development tool, to implement any of a vast choice of functions. The analogue peripherals may be configured to create customer analogue front-ends (AFEs) for sensors. The digital peripherals may be configured as communication interfaces, or as timers/counters/PWMs, or to implement glue logic.

In the PSoC 6 MCU architecture, these configurable peripherals are supported by essential system resources that are hard wired into the chip, such as:

• System memory
• An ARM Cortex-M processor core
• I/Os and programmable interconnects and routing

Commonly used peripherals, such as a USB interface and CapSense capacitive sensing technology, are also pre-integrated into PSoC devices.

Earlier products such as the PSoC 4 and PSoC 5 have found uses in a wide variety of applications that benefit from:

• The flexibility of the programmable architecture, which makes it easy to change system functionality at any point in the development process without having to re-spin the board layout.
• The wide choice of high-performance analog interfaces and functions.

With PSoC 6, however, Cypress has purpose-built PSoC for the IoT with the aim of providing capabilities and attributes better than any currently available to microcontroller users. This ground-up rethinking of the PSoC’s fabric started with process technology - PSoC 6 is the first PSoC to be made with 40nm technology, an ultra-low-power process node.

Figure 1: PSoc Dual-Core MCU architecture example

Cypress has also introduced an architectural first in PSoC 6, a dual-core device which features a high performance ARM Cortex-M4 core operating at up to 150MHz, and a low power ARM Cortex-M0+ core (see Figure 1). The implementation of these cores at the 40nm process node provides best-in-class power and performance. The PSoC 6 provides a Low-Power Active mode in which the ARM Cortex-M4 core draws as little as 22µA/MHz, and the ARM Cortex-M0+ just 15µA/MHz. In competing microcontrollers also based on the ARM Cortex-M4 core, Active mode current is commonly more than three times as high.

The power benefits of this flexible architecture extend further, of course, because it also allows for intelligent partitioning of system functions. In a device such as a wireless sensor, for instance, sensor interface or sensor hub functions which have a low computational intensity but which must be always on can run in the ARM Cortex-M0+ core while the high power ARM Cortex-M4 core sleeps. Periodically, the ARM Cortex-M4 core can wake up to quickly perform intensive processing tasks, such as processing batches of sensed data before transmission to a cloud server. PSoC 6 also implements dynamic frequency and voltage scaling to enable optimisation of power and throughput.

This partitioning of functions allows a single chip to combine high processing capability and high performance with ultra-low power consumption.

Secure memory on-chip
Architectural and process breakthroughs, then, deliver the power/performance combination required in many always-on IoT end node applications. The IoT also requires a critical security capability to protect data, user privacy, systems and networks.

In PSoC 6, this is enabled by a Trusted Execution Environment (TEE) which provides multiple, simultaneous on-chip secure memory zones hosting ‘trusted applications’. The TEE offers scalable, secure memory and processor resources for the implementation of multiple, independent user defined security policies, without the need for external secure memories or secure elements.

PSoC 6 also supports industry standard cryptographic algorithms including ECC and AES in integrated hardware co-processors, and provides secure, internal storage for firmware, applications and secure assets such as cryptographic keys. Secure storage is protected by an eFUSE which when blown disables the debug pin so that the contents of the secure memory cannot be read by a debugger.

PSoC 6 also implements an optional secure boot process by which the application image is authenticated against an image stored in a secure on-chip memory location.

On-chip wireless connectivity
PSoC 6 also provides for the connectivity requirements of the latest IoT designs. In the PSoC 63 series, users can choose a part optimised for wireless or wired connectivity, which offers an on-chip USB 2.0 interface and PHY, or a part optimised for BLE which includes an on-chip 2.4GHz RF transceiver and BLE 5.0 support. This BLE part, which also provides CapSense capability and analogue peripherals including two op amps, two comparators, a 12-bit ADC and a 12-bit DAC, offers capabilities that would typically in previous designs have required four ICs - a high performance microcontroller, a BLE RF chip, a low power sensor controller and a touch sensing controller.

Resources for evaluation and design
The combination of ultra-low-power operation, high processor performance, security functions and on-chip connectivity in the PSoC 6 are, then, ideally suited to the needs of tomorrow’s IoT edge nodes. Designers who wish to evaluate these capabilities can do so with the PSoC 6 BLE Pioneer Kit (part number CY8CKIT-062-BLE), which will be available later in 2017. The board (see Figure 2) features a dual-core PSoC 6 BLE, on-board antenna, Capsense slider, buttons and proximity sensor, USB Type-C controller and connector, and headers for Arduino Uno shields.

Figure 2: PSoC 6 BLE Pioneer Kit CY8CKIT-062-BLE