SoC-friendly clock family reduces board space by 90%

8th October 2014

IDT

Staff Reporter

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A SoC-friendly, PCIe timing family has been expanded with the introduction of 1.5 V clock generators and clock multiplexers. IDT's latest additions join the previously introduced 1.5 V buffers to provide enterprise-level performance for space- and power-constrained designs. The company claim that the chips offer up to a 90% reduction in power and board space compared to standard 3.3 V current-mode HCSL devices.

Delivering two, four, six or eight outputs, the 9FGU clock generator family is offered with and without internal terminations. This gives designers a choice of a flexible termination or minimal board space with integrated terminations, for 100Ω transmission lines. All devices are pin-compatible with the company's 1.8V 9FGV PCIe G123 clock generator family.

The 1.5V 9DMU and pin-compatible 1.8V 9DMV clock multiplexers are two-input devices with either one or four outputs. These clock multiplexers are offered with a choice of external terminations or integrated 100Ω terminations, and feature a choice of switchover modes. The user can choose between asynchronous switching or synchronous switching modes.

The entire family supports PCIe Gen1, Gen2, and Gen3 (Gen 1-2-3) phase jitter requirements. The chips are suited for use in DSLR cameras, multi-function printers, solid state drives, vehicle infotainment systems, servers, micro-servers, set-top boxes, PCIe-based storage arrays, and a variety of other PCIe-based applications.

“Our PCIe family of 1.5 V generators, buffers and multiplexers deliver industry-leading features that align with our customers’ needs to reduce space and power,” said Dave Shepard, vice president and general manager of IDT’s timing and RF division. “As the latest addition to our broad PCIe timing portfolio, this new family of devices delivers power at less than 30 milliwatts, lowering cost of ownership and virtually eliminating thermal concerns.”