Quad-channel clock translator synchronises SONET/SDH

20th May 2014

Analog Devices

Caroline Hayes

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Datasheet

PCIM 2014: Jitter clean-up and synchronisation for systems, including synchronous optical networks is provided with the AD9554 multi-service adaptive quad-channel clock translator with clock multiplier from Analog Devices. An embedded cross-point switch at the input is more flexible, says the company, and has a lower cost of ownership, compared with maintaining different clocking configurations of multiple parts.

The translator dissipates only 940mW while generating up to eight output clocks over an output range of 430kHz to 941MHz, synchronised to four 2kHz to 1GHz external input references, with a loop bandwidth down to 0.1Hz.

The device bridges the analogue-digital divide, with four analogue-digital PLLs which reduce the input jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output clock even when all reference inputs have failed, says the company. An adaptive clocking capability allows the user to dynamically change the DPLL divide ratios while they are locked.

System costs are reduced through simplified clocking circuitry brought about by the level of integration, adaptive clocking capability, and optical transport network (OTN) mapping algorithm embedded in DPLL, claims the company. Output jitter is 250fs over the 50kHz to 80MHz range and 350fs over the 12 to 20MHz range.

Ethernet protocols ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261, and ITU-T G.8262 are supported.