Packet network sync clock combines performance & low power

The Si5348 clock is also suitable for general-purpose frequency translation for wireless and telecomms infrastructure, broadband networks (e.g., G.fast DSL and PON) and data centre applications.

SyncE and IEEE 1588 have become increasingly popular methods to deliver synchronisation over packet networks. As these technologies become more widespread, networking equipment designers are demanding more flexible, cost-effective timing solutions that easily integrate into existing hardware architectures. Conventional network synchroniser clocks rely on rigid synchronisation clock chip architectures that borrow heavily from legacy Stratum 3 clock ICs, which are not optimised for size, power or performance.

The Si5348 clock delivers a solution that is 50% smaller, 35% lower power and 80% lower jitter than conventional synchronisers. These benefits enable hardware designers to simplify the adoption of packet network synchronisation without compromising system-level performance. The Si5348 architecture leverages Silicon Labs’ proven 4^th-gen DSPLL technology to deliver best-in-class jitter performance in a timing solution that is fully compliant with IEEE 1588, SyncE and Stratum 3 clocking requirements, enabling the device to be used in a wide variety of timing card and line card clock architectures. The Si5348 clock has been designed to easily interoperate with IEEE 1588 software running on an external host processor, further simplifying system integration.

“Networks are transitioning from circuit-switched to packet-switched systems to increase efficiency, flexibility and cost effectiveness, and as SyncE and IEEE 1588 become more widely adopted, equipment makers are looking for solutions that minimise the cost and complexity of adding packet network synchronisation to a design,” said James Wilson, Marketing Director, Timing Products, Silicon Labs. “Silicon Labs’ Si5348 packet network synchroniser clock provides best-in-class jitter performance, frequency flexibility, power efficiency and footprint, enabling hardware developers to optimise their designs with a clock-tree-on-a-chip solution.”

In packet timing applications, high-stability oscillators play a critical role in defining the network’s overall performance in terms of frequency, time and phase accuracy. Network topologies often will dictate the type of Temperature-Controlled crystal Oscillator (TCXO) or Oven-Controlled crystal Oscillator (OCXO) required at each node in the network. The Si5348 clock supports a universal reference input port, enabling the device to be paired with any frequency TCXO/OCXO.

As part of the Si5348 product development, Silicon Labs has partnered with Rakon to deliver a combined solution that can be used across a broad variety of SyncE and IEEE 1588 applications. “Rakon offers the industry’s widest portfolio of TCXOs and OCXOs for SyncE and IEEE 1588 applications,” said Ullas Kumar, Application Marketing Manager, Rakon. “By partnering with Silicon Labs, we offer customers a timing solution that can be easily optimised at the application level in terms of frequency, stability, aging and cost while ensuring compliance with ITU-T standards for MTIE and TDEV requirements.”

Factory pre-programmed samples and production quantities of the Si5348 network synchroniser clock are available now in a 9mm² QFN package. Si5348 pricing in 10,000-unit quantities ranges from $10.00 to $12.00, depending on output frequency. Silicon Labs’ Si5348-EVB evaluation board, priced at $399 (MSRP), enables developers to move quickly from device configuration to detailed performance analysis to custom part number generation in less than five minutes. ClockBuilder Pro software is available from Silicon Labs’ website to ease the configuration and evaluation of the Si5348 clock.