Output fanout buffers experience 200fs of additive jitter

The flexible outputs allow engineers to use a single device to meet the requirements of systems utilising multiple signal types, which can translate to reduced costs and space savings by reducing the number of required components. The devices can accept any level clock input and generate any level output. Users can specify the signal type and voltage of each output on the buffer, meaning a single device can, for example, supply LVPECL on one output, LVDS on another, and LVCMOS on a third.

The output fanout buffers are well suited for a wide array of applications, including products for high-end consumer, networking, computing, industrial, communications and broadcast video.

“Our family of universal output fanout buffers delivers extremely low jitter and enables our customers to use a single buffer device to deliver the different output types needed to meet the requirements of SoCs and FPGAs,” said Dave Shepard, Vice President and General Manager, Timing and RF Division, IDT. “By adding these capabilities to IDT’s timing portfolio, our customers can reduce their BOM by utilising one buffer device with multiple boards and applications.”

With the IDT 5P11xx family of buffers, clock outputs can be individually programmed as LVDS, LVPECL, HCSL or two LVCMOS outputs per output pair, with a crystal, LVCMOS or differential input. The chips enable four universal output pairs, as well as a reference LVCMOS output clock. Output frequencies range from 1 to 200MHz for LVCMOS and 1 to 350MHz for differential outputs. Output voltage can be individually selected (1.8, 2.5 or 3.3V) for each output pair. The 5P1103 has two universal outputs and an LVCMOS output; the 5P1105 has four universal outputs and an LVCMOS output.