Optimum SNR with low jitter clocks

This enables the LTC6954 to deliver the low jitter clocks necessary to achieve optimum SNR when driving high resolution data converters. Low jitter ADC clocking, for instance, is especially crucial when digitising high analogue frequencies such as RF or high IF signals, making the LTC6954 well suited for clocking solutions in such systems.

The LTC6954 family includes four versions, offering various combinations of LVPECL and LVDS/CMOS output logic drives. This provides the flexibility to optimally connect to a large number of devices accepting different logic signals. Powered from a single 3.3V supply and programmed through SPI, the LTC6954 independently divides the input clock by any integer between 1 and 63, and also provides the capability to independently delay each of its outputs by 0 through 63 input clock cycles. This facilitates the creation of phase shifted clocks necessary, for instance, for driving the ADCs of the I- and Q-channels in communications systems.

In addition to its capability as an independent clock distributor, the LTC6954 features Linear Technology’s propriety EZSync synchronisation method. Triggered by a pulse, EZSync synchronisation aligns the rising edges of multiple outputs from one or multiple chips to produce repeatable and deterministic phase relationships between all clock divider outputs. The LTC6954 can pair up with the LTC6950 as a follower to expand the number of low jitter edge aligned clock outputs generated by the LTC6950.

The LTC6954 is specified over the full operating junction temperature range of -40 to 105°C and is offered in a 4x7mm, 36-lead plastic QFN package.