First VPX backplane to support radial clock slot card released

Unique to this backplane is its support of high speed signals on all the data paths as well as leading edge VITA 67.3 connectors compatible with legacy VITA 67.1 and VITA 66.4 RF and optical I/O connectors.

Ken Grob, Director of Embedded Computing Development, said “This latest backplane incorporates new VPX features, unmatched by any other embedded backplane architecture to date, that will allow the VPX architecture to address a range of applications.”

This is the first VPX backplane with a radial slot card for timing and synchronisation. The 3U, 12-slot backplane includes 7 slots that receive radial clock signals (Aux Clk and Ref Clk) driven independently from a radial clock timing card. The remaining 5 slots receive standard VPX bussed Aux_Clk and Ref_Clk signals. The timing card slot also supports a VITA 67.3c connector with 10 SMPM cavities.

The backplane can handle the highest data rates possible with the VPX connector through its multiple data plane UTP connections at 10GBASE-KR data rates and 10GBase-KR UTP control plane connections.

Four payload slots, each equipped with a combination VITA 67.3c optical and RF connector in the J2 position are also featured on the backplane. The slot 2 switch supports a VITA 67.3d connector module compatible with a payload module fitted with a VITA 66.4 MT optical ribbon connector or a VITA 67.1 RF coaxial connector.

When equipped with optical interfaces, the VPX architecture now allows data rates across the backplane far greater than any copper interconnect can be expected to achieve with the additional benefit of lower design complexity. The VPX optical interface ensures that this backplane will be able to meet all future bandwidth requirements.

Also included on the backplane is a 12-cavity, VITA 67.3e connector to support an RF switch card. The new VITA 67.3 connectors allow high speed optical and RF interfaces present on payload modules to be mated and removed from the backplane. The scheme allows different types of I/O cabling routed to a slot to remain connected to the rear of the backplane to distribute interfaces.

The backplane has two additional slots for plug-in power supplies but is also designed with power input threaded studs so either power input method can be used. The backplane can be supplied in a mini ATR style chassis.

Designed to align with the DOD’s Hardware/Software Convergence Initiative, which aims to develop a common, modular hardware architecture across C4ISR and EW systems, the backplane contributes to optimized size, weight and power requirements and lower lifecycle costs to enable rapid technology insertion for the soldier.