Clock synthesiser provides 86fs RMS phase jitter

24th November 2014

IDT

Siobhan O'Gorman

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Datasheet

A high-performance synthesiser with ultra-low phase jitter for reducing bit error rates in today’s serial data communications systems has been introduced by Integrated Device Technology (IDT). Featuring an integrated fanout buffer/divider, the 8T49NS010 delivers high-performance clocks for demanding applications and is suitable for 40 and 100GE telecommunications and networking systems.

The 10-output synthesiser provides a high-frequency clock with 86fs RMS phase jitter over the standard 1kHz to 20MHz integration range. The 8T49NS010 features an integrated fanout buffer, removing the issues of additive phase jitter and noise coupling from oscillator to fanout buffer. The chip supports programmable configurations and output levels to satisfy the requirements of a variety of applications.

The 8T49NS010 is configurable through an I2C serial interface and operates over an industrial temperature range. In addition to output power-down, the synthesiser supports two logic levels for its differential outputs; the first provides an LVPECL output level with 750mV typical swing, while the second provides a similar swing and output level with no external DC termination. The device uses an external fundamental mode crystal, alleviating the expense and availability issues associated with high-end oscillators.

“The 8T49NS010 synthesiser delivers ultra-low jitter required for high-speed communications,” said Louise Gaulin, Vice President and General Manager, Network Communications Division, IDT. “The device provides engineers with a simple, yet ultra-high-performance solution.”