Updated IP cores support various bus protocols

28th January 2014

Staff Reporter

0 0

Two IP cores, designed to provide a quality communication bus interface for military, commercial aviation and space applications, has been announced by Microsemi. The Core1553BRT v4.0 and Core1553BRM v4.0 IP cores support the company’s SmartFusion2 SoC FPGAs and IGLOO2 FPGAs, whilst also including enhancements for their currently supported FPGA families.

Based on MIL-STD-1553, the Core1553 supports various bus protocols such as Remote Terminal, Bus Controller and Monitor Terminal. Completed on SmartFusion2 SoC FPGAs, the updated cores were certified per the RT Validation Test Plan outlined in MIL-HDBK-1553 Appendix A.

The Core1553 IP features on the SOFIE scientific instrument of the AIM mission, whilst also featured onboard the COTS for the International Space Station. Future plans for the Core1553 IP include having flight heritage on the James Webb Space Telescope and Joint Polar Satellite System.

“Microsemi continues to provide aerospace solutions with the highest levels of quality and reliability by achieving certification and qualification not only for our devices, but also for the IP cores that help customers design with these devices,” commented Minh Nguyen, Microsemi’s marketing manager, space and aviation. “The updated Core1553BRT and Core1553BRM solutions enable customers to implement efficient and low resource-utilization data handling interfaces in our latest technology.”

The updated core IPs are avilable now. A SmartFusion2 SoC FPGA reference design and Core1553 Development Kit supporting SmartFusion2 devices will be available later in 2014.