TEWS adds advanced FPGA to XMC module range

A standard single-width Switched Mezzanine Card (XMC) compatible module, it adds higher performance and flexibility to the current XMC line for digital and analog applications. This groundbreaking module will transform complex industrial processes, ensuring a higher level of precision, speed, and adaptability in managing them.

“The TXMC639 was conceived to add performance and flexible features to the current XMC product line,” noted Jan Zimmermann, General Manager of TEWS Technologies. “For customers seeking to achieve higher performance, the TXMC639 extends many of the TXMC637 features with more memory, better channel density and configuration options, and the AMD Kintex 7.”

The TXMC639 provides a user configurable FPGA based on the Kintex 7 and is packed with up to 16 ADC input channels, providing single-ended or differential mode operation with a 16-bit resolution and speed as fast as 1.5 MSPS. Its programmable gain amplifier enables a full-scale input voltage range of up to +/-20.57V differential. For digital interfacing, it offers 32 programmable ESD-protected TTL lines. 16 of these TTL lines can be switched to 8 differential RS422 I/O lines via software control. The device boasts an integrated 1 GB, 32-bit wide DDR3L SDRAM with an SDRAM interface that is routed to a HP bank of User FPGA Kintex 7 for use with an Internal Memory Controller.

Included are 8 DAC output channels, based on the Dual 16-bit AD5547 DAC. They offer configurable single-ended bipolar analog outputs of up to +/-10V. The system also provides 64 FPGA I/Os on P14 and 4 FPGA Multi-Gigabit-Transceiver on P16 for customer-specific I/O extension or inter-board communication.

The TXMC639 finds its applications across a wide range of industries, including manufacturing, IT, and automation. Its in-built flexibility and robust features make it a solution of choice for complex process-management tasks.

User applications for the TXMC639 with Kintex 7 FPGA can be developed using the AMD Vivado design tool. A full (non-webpack) license for the Vivado Design Suite design tool is required, due to FPGA density. TEWS offers a well-documented FPGA Board Reference Design. It includes a constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the board.