Talking FPGAs with Enclustra

Enclustra's Mars ZX3 SoC combines Xilinx's Zynq-7020 All Programmable SoC (which consists of a dual-core CortexT-A9 ARM processor and an Artix-7 FPGA fabric) with fast DDR3 SDRAM, NAND flash, quad SPI flash, Gigabit Ethernet PHYs, USB and a real-time clock.

The Mercury KX1 FPGA provides the best performance-to-price-ratio Xilinx Kintex-7 FPGAs in conjunction with the latest high-speed standard interfaces such as USB 3.0, PCIe 2.0 and Gigabit Ethernet. It is suited for high-end digital signal processing, communications, networking and high-speed I/O applications.

The company's Mars AX3 FPGA module is suited for high-speed communication and DSP applications with a powerful, low-cost Xilinx Artix-7 FPGA, Gigabit Ethernet and fast DDR3 SDRAM. The FPGA's 68x30mm SO-DIMM form factor enables space-saving hardware designs as well as speedy and simple integration into the target application.

Suited for digital signal processing, networking, high-speed I/O and SoPC applications utilising the Altera Nios II soft processor, the Mercury CA1 module offers high-performance yet low cost Altera Cyclone IV FPGAs in conjunction with standard interfaces. It features powerful standard interfaces, many LVDS capable I/Os, large DDR2 SDRAM and hardware multipliers.

Enclustra’s FPGA Manager IP solution allows for easy and efficient data transfer between a host and a FPGA over different interface standards. Featuring a a host software library (DLL), a suitable IP core for the FPGA and device controller firmware, the user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. Additionally, streaming and memory-mapped accesses are supported.

Entirely written in VHDL, the easyIRT Profinet communication controller IP Core supports advanced features like Dynamic Frame Packing and allows cycle times down to 31.25µs. The Profinet IRT IP core can easily be combined with other IP cores to build entire SoC solutions.

Enabling the easy addition of drive control capabilities to existing or future FPGA designs, the Universal Drive Controller IP Core from Enclustra will significantly reduce time to market as well as the overall system cost. There is no need for an extra drive controller chip that would consume precious PCB space and unnecessarily extend the project BOM.