Speedcore embedded FPGAs reduce power by half

Speedcore eFPGA products are fully supported by Achronix’s robust and proven ACE design tools. With Speedcore, customers specify the optimal die size, power consumption and resource configuration required for their end application. Customers define the quantity of look-up-tables (LUTs), embedded memory blocks and DSP blocks. Additionally customers define the Speedcore aspect ratio, IO port connections and can make tradeoffs between power and performance. Achronix delivers a GDS II of the Speedcore IP that customers integrate directly into their SoC, and a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA.

“Over the years, different companies have talked about eFPGA products, but Achronix Speedcore is the first eFPGA IP to ship to end customers, and it is a game changer” said Robert Blake, President and CEO, Achronix Semiconductor. “Achronix was the first company to deliver high density FPGAs with embedded system level IP. We are using that same proven methodology to deliver our eFPGA technology to customers who want to combine all the efficiencies of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same chip.”

“Designers have long sought the inherent advantages that could come from embedding FPGA functionality as IP into SoCs for a host of different high performance applications,” said Richard Wawrzyniak, Principal Analyst for ASIC and SoC at Semico Research Corp. “Achronix has now delivered eFPGA IP to customers who are developing high-performance computing products where offloading compute intensive functions from processors to FPGA IP can provide a tremendous performance boost. While an exciting opportunity for Achronix, seeing FPGA IP become a reality is great news for the semiconductor industry, particularly when you consider the large market opportunity for compute high-performance applications.

Speedcore is the optimal hardware accelerator compute and communications infrastructure in data centres and entreprises can no longer keep pace with exponential data growth rates, changing security and software virtualisation requirements. Traditional multi-core CPUs and SoCs need programmable hardware accelerators that pre-process and offload data to increase their compute performance. FPGAs are the optimal hardware accelerator solution because accelerators need to be updated with functionality as algorithms are constantly changing. Standalone FPGAs are a convenient and practical solution for low to medium volume applications, whereas Speedcore is the optimal solution for high volume applications and offers significant advantages:

Lower power:

• Speedcore has direct wire connections to the SoC, which eliminates the large programmable IO buffers found in standalone FPGAs. Programmable IO circuitry accounts for half of the total power consumption of standalone FPGAs.
• Speedcore is sized exactly to the requirements of the customer’s end application.
• Customers can tune the process technology to tradeoff performance for lower power.

Higher interface performance:

• Speedcore offers dramatically higher interface performance than standalone FPGAs in the form of lower latency. Speedcore is connected to the ASIC through an ultra wide parallel interface whereas standalone FPGAs typically connect through a high latency SerDes structure.

 Lower system cost:

• Speedcore die size is much smaller than standalone FPGAs because the programmable IO buffer structure is eliminated.
• Standalone FPGAs have high pin counts which dictate the PCB layer count to support the FPGA BGA package escape routing. Additionally, Speedcore eliminates the need for all of the support components around the FPGA including power regulators, clock generators, level shifters, passive components and FPGA cooling.

Higher system reliability and yields:

• Integrating FPGA functionality into an ASIC improves system level signal integrity and eliminates reliability and yield loss associated with having a standalone FPGA on the PCB.