Software evaluates FPGAs and SoCs

The design tool’s latest release includes enhancements such as mixed language simulation, a new netlist viewer and what the company describes as best-in-class debugging capabilities. The company is also introducing a free evaluation license enabling users to evaluate its flash-based FPGAs and SoC FPGAs.

The Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator, allowing line by line verification of hardware description language (HDL) code. Simulation can be performed at behavioural (pre-synthesis), structural (post-synthesis), and back-annotated, dynamic simulation levels. A GUI enables quick identification and debug of problems, it says. The suite now includes ModelSim Microsemi Pro for customers to simulate in mixed language environments as well as 20% runtime improvement in recent versions of the tool.

ModelSim ME Pro provides mixed language simulation support for VHSIC Hardware Description Language (VHDL), Verilog and SystemVerilog. Customers can target a range of IP designs without worrying about mixing languages, says the company. SmartDebug enhancements, such as the FPGA Hardware Breakpoints (FHBs), enable users to set breakpoints in designs and step by clock cycle, providing significant visibility and “significant reduction” in debug time.

Breakpoints, historically used in embedded software, can now be used to support FPGA logic debug functions. This increases productivity, usability and efficiency, resulting in faster time to market, particularly in the product validation phase, the longest cycle of product development. SmartDebug enhancements complement existing debug capabilities to debug FPGA devices’ status, memory and serialiser/deserialiser (SerDes) transceivers without using an integrated logic analyser (ILA).

The tool is suitable for FPGA designs targeting applications in aerospace, defence, security, communications, data centre, industrial and automotive markets. A netlist viewer, a new feature, provides visibility into different internal structures. There are also new constraints management features offering block flow and an I/O adviser, 20% runtime improvements for its SmartTime user interface and Windows 10 OS support.

There is a new 60-day evaluation license which can be used to evaluate Microsemi flash-based FPGA and SoC reference designs, tutorials and application notes.

Libero SoC v11.8 features the company’s Secured Production Programming Solution (SPPS), which generates and injects cryptographic keys and configuration bitstreams to prevent overbuilding, cloning, reverse engineering, malware insertion and other security threats.