Safety package combines FPGA with lockstep processor solution

24th November 2015

Altera Europe

Jordan Mulcare

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Altera Corporation has announced the availability of the Altera Functional Safety Lockstep solution for the Nios II embedded processor, a solution that reduces risk in design cycles and helps system designers simplify certification for industrial and automotive safety applications. The joint Altera and YOGITECH lockstep solution is built using Altera FPGAs, SoCs, and certified tool flows, along with IP cores from YOGITECH, a functional safety leader based in Pisa, Italy.

This solution enables customers to easily implement SIL3 safety designs in Altera FPGAs, including the low-cost Cyclone V FPGA and MAX 10 FPGA families. The solution is being demonstrated at the SPS IPC Drives conference in Nuremberg, Germany, from the 24^th to 26^th of November,at the Altera stand (Hall 3, Stand #270).

The lockstep solution leverages YOGITECH’s industry-leading fRSmartComp technology to provide high diagnostic coverage, self-checking and advanced diagnostic features for safety-related integrated circuits, in full compliance with functional safety standards IEC 61508 and ISO 26262. The fRSmartComp technology, which is used in conjunction with Altera’s flexible Nios II embedded processors, provides diagnostic coverage greater than 99% without the need for difficult-to-develop ad hoc tests, speeding time-to-market.

“Developing systems based on products that already comply with the stringent safety requirements and standards required for industrial applications makes our customers’ design challenges easier,” said Roger May, System Architect and Functional Safety Lead, Altera. “This lockstep solution enables designers to take advantage of the flexibility of the already-certified Nios II processor to quickly bring their solution to market while meeting strict safety requirements, reducing risk in design cycles.”

“Thanks to the detection, self-checking and diagnostic features provided by our proven fRSmartComp technology, system developers can meet safety standards and increase availability,” said Silvano Motto, CEO, YOGITECH. “The IP is delivered with the documentation required to comply with functional safety standards, speeding time-to-market for designers and consequently reducing costs. I am very proud to announce our fRSmartComp solution is now available to Altera FPGA users.”