Programmable logic innovations double performance

The ability to achieve double the core logic performance also enables dramatic improvements in device utilisation and power by reducing the need for very wide data paths and other skew-inducing design constructs required by competing architectures. The HyperFlex architecture enables high-performance designs to operate at up to 70% lower power by reducing logic area requirements.

All members of the Stratix 10 FPGA and SoC family leverage heterogeneous 3D SiP integration to efficiently and economically integrate a high-density monolithic FPGA core fabric (up to 5.5m logic elements) with other advanced components, thereby increasing the scalability and flexibility of the devices. A monolithic core fabric maximises device utilisation and performance by avoiding the connectivity issues of competing homogeneous devices that use multiple FPGA die to deliver higher densities. Altera’s heterogeneous SiP integration is enabled through the use of Intel’s proprietary embedded multi-die interconnect bridge technology, which provides higher performance, reduced complexity, lower cost and enhanced signal integrity compared to interposer-based approaches.

Stratix 10 FPGAs and SoCs will feature the industry’s most comprehensive security capabilities in a high-performance FPGA. At its core is an innovative secure design manager which delivers sector-based authentication and encryption, multi-factor authentication and physically unclonable function technology. Altera has partnered with Athena Group and IntrinsicID to deliver world-class encryption acceleration and PUF IP for Stratix 10 FPGAs and SoCs. This level of security makes Stratix 10 FPGAs and SoCs suitable for use in military, cloud security and IoT infrastructure, where multi-layered security and partitioned IP protection are paramount.

Altera’s Spectra-Q engine within the Quartus II software is designed to maximise the performance, power and area saving benefits the HyperFlex architecture provides, while improving designer productivity and time-to-market for Stratix 10 FPGAs and SoCs. The Quartus II software extends Altera’s software leadership with new capabilities that will deliver up to 8 times faster compile times, versatile and fast-tracked design entry, drop-in IP integration and support for OpenCL and other higher-level design flows.

Danny Biran, Senior Vice President of Marketing, Altera, commented: “The capabilities that we offer in Stratix 10 FPGAs and SoCs are truly unmatched in the industry. Stratix 10 FPGAs and SoCs enable our customers to design their systems and innovate in ways that were previously not possible in an FPGA.”

Customers can get started on their Stratix 10 designs now using the Fast Forward Compile performance evaluation tools. Engineering samples of Stratix 10 FPGAs and SoCs will be available in the fall of 2015. Embedded software developers can leverage SoC virtual platforms from Mentor Graphics to accelerate Stratix 10 SoC embedded software development.