Pentek adds VITA 49 protocol engine to cobalt FPGA boards

“VRT is the future of software defined radio," said Paul Mesibov, Pentek’s VP of Engineering. "The protocols defined in VRT provide data and context packets that standardize the way information is transported from radio to signal processing equipment. Pentek has invested heavily in supporting the definition of VRT." Pentek is a co-sponsor and key contributor to the VITA 49 standards development effort.

The VITA Radio Transport (VRT) standard defines a transport-layer protocol for data and context packets designed to promote interoperability between RF (radio frequency) receivers and signal processing equipment in a wide range of communication and radar systems. The VRT protocol provides a variety of formatting options that allow the transport layer to be optimised for each application. VRT enables high-precision timestamping to provide time synchronization between multiple receiver channels. Context packets can capture very precise context for each signal, including antennae gain and azimuth, frequency, spatial location, temperature and more.

The VITA 49 specification addresses the problems of interoperability between elements of Software Defined Radio (SDR) systems. Previously, each SDR receiver manufacturer developed custom and proprietary digitised data and meta-data formats, making exchange of data from different receivers challenging. With a common protocol, SDR receivers can be interchanged, enabling hardware upgrades and mitigating hardware lifecycle limitations, without the need to create new software to support each new receiver.

A front end A/D converter stage accepts four analogue HF or IF inputs on front panel SSMC connectors, with each transformer-coupled to Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The 200 MHz sampling rate handles the needed bandwidth for a wide range of signal processing applications.

The Model 71664 comes preconfigured with a suite of built-in functions for digital down conversion, data capture, synchronisation, time tagging, and formatting, making them suitable turn-key interfaces for radar, communications or general data acquisition applications. IP modules for A/D acquisition, DDC, DDR3 or QDRII+ memories, programmable beamforming, controller for data clocking and synchronisation and a VRT protocol engine are all included.

Pentek offers both PC and VPX SPARK development systems, so designers can start immediately on application platforms. Created to save engineers and system integrators the time and expense associated with building and testing a system, SPARK ensures optimum performance of Pentek boards.

The Pentek ReadyFlow Board Support Package is available for Windows and Linux operating systems. ReadyFlow is provided as a C-callable library, a complete suite of initialisation, control and status functions, as well as a rich set of precompiled, ready-to-run-examples, to accelerate application development. Extensions to support VITA 49 are included in the BSP.

For systems that require custom functions, IP can be developed using the Pentek GateFlow FPGA Design Kit, extending or even replacing the factory-installed functions. Software support packages are available for Linux and Windows operating systems.