FPGA transceiver to enable 400G Ethernet deployment

At the Optical Fibre Communications (OFC) conference in San Diego this week, Intel’s Programmable Solutions Group is showcasing 58Gbps transceiver technology integrated on the Intel Stratix 10 TX FPGA - the first Field Programmable Gate Array (FPGA) with 58Gbps PAM4 transceiver technology now shipping in volume production and enabling 400Gb Ethernet deployment.

“As we continue to deliver product innovations and capabilities that allow for higher data ingest and processing speeds critical for networking and data centre applications, this is a powerful example of how Intel FPGAs bring real value to our customers.” said Dan McNamara, Intel Senior Vice President and General Manager of the Programmable Solutions Group.

This technology doubles transceiver bandwidth performance when compared to traditional solutions. It is critical for applications where high bandwidth is paramount, including: networking, cloud and 5G applications, optical transport networks, enterprise networking, cloud service providers, and 5G. By supporting dual-mode modulation, 58Gbps PAM4 and 30Gbps NRZ, new infrastructure can reach 58Gbps data rates while staying backward-compatible with existing network infrastructure.

The Stratix 10 TX FPGA with 58Gbps PAM4 transceiver technology provides system architects with higher transceiver bandwidth and hardened IP to address the insatiable demand for faster and higher density connectivity.

“The 400Gb Ethernet and QSFP-DD market is evolving at a fast pace. And being first to market with a portable solution is instrumental to enable the transition from lab to the field. We were excited to work closely with Intel to deliver our next-gen test module with the only production FPGA technology supporting native 58Gbps PAM4,” said Ildefonso M. Polo, Vice President of Product Marketing at VeEX.

To facilitate the future of networking, Network Function Virtualisation (NFV) and optical transport solutions, Intel Stratix 10 TX FPGAs provide up to 144 transceiver lanes with serial data rates of 1-58Gbps. This combination delivers a higher aggregate bandwidth than any current FPGA, enabling architects to scale to 100Gb, 200Gb and 400Gb delivery speeds.

A wide range of hardened intellectual property cores, including 100Gb MAC and FEC, deliver optimised performance, latency and power.

Intel Stratix 10 FPGA 58Gbs transceivers are interoperable with 400G Ethernet FPGAs, using only eight channels to support new high bandwidth requirements for routers, switches, active optical cables and direct attach cables, interconnects, and test and measurement equipment.

At Intel Architecture Day, Intel unveiled a 112G PAM4 high speed transceiver test chip built on 10nm process technology. The chip will be incorporated into Intel’s next-gen FPGA product families, supporting the most demanding bandwidth requirements in next-gen data centre, enterprise and networking environments.