FPGA logic architecture features Block RAM & DSP cores

Flex Logix’s EFLX technology allows SoC designers to embed FPGA into complex chip designs. The inclusion of FPGAs into a SoC enables key functions to be optimised or customised after the device is completely fabricated, even updating logic after a device is installed into a system in the field.

By adding BRAM and DSP, the company expands the tool kit available to designers for this post-production flexibility. For instance, applications such as encryption, networking and signal processing require blocks of RAM to be integrated into the FPGA to provide fast local memory to implement buffers, scratchpads, FIFOs, and other low-latency memory that improves performance.

While traditional FPGAs typically offer one type and size of RAM that can ‘emulate’ different widths, Flex Logix’s Block RAM architecture can provide exactly the type and amount of memory an application requires. This flexibility is accomplished by inserting BRAM between the EFLX logic cores, which ‘tile’ together to make an array, controlling them with otherwise unused inward-facing inter-tile I/Os. The company can support single-port RAM or dual-port RAM, any width, any amount; ECC, parity or no error checking; even MBIST, offering far more flexibility than available in traditional stand-alone FPGA chips.

In addition to local memory, many applications also require DSP capability. Wireless base station digital front ends, image and audio processing, and other applications require high-performance DSP functions such as Finite Impulse Response filters, Infinite Impulse Response filters, and Fast Fourier Transforms.

The basic building block for implementing these DSP functions is a pre-adder/multiplier/accumulator (MAC). Flex Logix now offers an EFLX Logic core that incorporates 40 MACs with 22-bit inputs and 48-bit accumulation. The MACs can be combined for two times precision and pipelined for high throughput. They can also be used as complex-number MACs for certain DSP algorithms.

Performance specs for a single Flex Logix DSP core are similar to that of existing stand-alone 28nm FPGA chips, achieving 500Msample/s for a 22-bit five-tap FIR and 300Msamples/s for a 22-bit 40-tap FIR. Multiple EFLX DSP cores can be combined to implement more complex DSP functions.

The EFLX Compiler maps standard Verilog/RTL into the EFLX array, including DSP and Block RAM. Customers do not require any FPGA expertise to use Flex Logix technology.