FPGA design software reduces compile times by 70%

The new Rapid Recompile feature is included with the software. Ideal for making small source code changes on Altera Stratix V FPGA designs, Rapid Recompile allows customers to reuse previous compilation results to preserve performance. Without the need for up-front design partitioning, this offers an additional 50% compile time savings.

Alex Grbic, director, software and IP product marketing, commented: “Our Quartus II software has been able to evolve with each generation of FPGA products because of our superior and proven software architecture that was designed right the first time. With new capabilities and enhancements to the latest version of the Quartus II software, we are delivering a 2X compile time advantage and a 20 percent performance advantage over the competition with our high-end FPGAs.”

Automatically connecting IP functions and subsystems, the Altera Qsys system integration tool saves significant time and effort throughout the FPGA design cycle. Designers can use Qsys to seamlessly integrate a mix of industry-standard interfaces, including Avalon, ARM AMBA AXI, APB and AHB interfaces, for faster system development. Enhanced system visualization further improves productivity, allowing multiple simultaneous views of the Qsys system. With Altera Qsys, it is significantly easier to modify the system, either by adding or connecting components to new a peripheral.

The industry’s only FPGA OpenCL solution to pass conformance testing by adhering to the OpenCL specification defined by the Khronos Group, Altera SDK for OpenCL is now in full production. It provides a software-friendly programming environment to design high-performance systems that use FPGAs on Altera’s Preferred Board Partner Program boards or Altera SoCs when using the Altera Cyclone V SoC development board.

Altera DSP Builder Design Tool enables system developers to effectively implement high-performance, fixed- and floating-point algorithms into their digital signal processing designs. Altera DSP Builder Advanced Blockset systems can now be integrated within MathWorks HDL Coder. This provides more options and flexibility to engineers during the design phase. Offering unprecedented performance and flexibility options to those implementing this common DSP function, improvements in fast Fourier transform processing include variable-sizing of FFTs at run-time and super-sampling FFTs for extremely high data rates of 10GHz.

With 70% lower latency and 50% resource utilization reduction, Quartus II software version 13.1 includes Altera’s best-in-class IP which maintains customer’s performance and throughput of the most heavily used and highest performance IP. These IP cores cover 10G, 40G and 100G Ethernet, and 25G to 150G Interlaken.

Quartus II software v13.1 is available for download now in a Subscription Edition and a free Web Edition. Altera design software can easily be obtained with Altera’s software subscription program, which consolidates software products and maintenance charges into one annual subscription payment. At just $2,995 (USD) for a node-locked PC license, subscribers receive Quartus II software, the ModelSim-Altera Starter edition, and a full license to the IP Base Suite, which includes Altera’s most popular IP (DSP and memory) cores.