FPGA board with TCI6638 multicore DSP+ARM

7th September 2018

VadaTech Ltd

Enaie Azambuja

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Datasheet

VadaTech has announced the AMC541. The AMC541 couples Xilinx Zynq Ultrascale+ XCZU19EG MPSoC FPGA with the TCI6638K2K communications KeyStone SoC to provide a high performance wireless infrastructure module. Zynq Ultrascale+ XCZU19EG MPSoC FPGA includes embedded Quad-core ARM Cortex-A53 application processing unit, Dualcore ARM Cortex-R5 real-time processing unit, ARM Mali - MP2 GPU.

The FPGA has Dual banks of 64-bit DDR4 memory (one bank to the ARM Core and one bank to the FPGA) and includes an SD card. The TCI6638K2K communications infrastructure KeyStone SoC is a member of the C66x family based on TI’s new KeyStone II Multicore SoC Architecture designed specifically for high-performance telecommunication, IoT and networking applications. It features eight TMS320C66x DSP core subsystems (C66x CorePacs). The TMS320C66x interfaces to dual 64-bit wide DRAM DDR-3.

The flexible AMC541 architecture allows the FPGA and DSP to interface to the AMC connector in different configurations. The AMC connector ports 2-3 and 8-11 are linked directly to the FPGA for the core to interface with the host through protocols such as SRIO, PCIe or 10/40GbE.

The ports 4-7 can connect directly to the FPGA in addition to ports 8-11, or connect directly to the DSP with SRIO protocol via MUX (DIP-switch selection). The module also routes GbE on ports 0 and 1 per AMC.2 and the DSP and FPGA are linked via PCIe x2 and GbE.

The on-board, re-configurable FPGA interfaces to the AMC FCLKA (fabric clock) and TCLKA-D (user clocks and triggers) via a clock and jitter cleaner. There is also a front panel TRIG IN and CLK IN to the clock and jitter cleaner – the three front panel SFP+ cages allow expansion via fiber or copper interface.