DCD’s HDLC/SDLC controller aims telecommunication

No matter if it’s 8-, 16- or 32-bit microcontroller, the DHDLC IP core can control HDLC/SDLC transmission frame,. The greatest advantage of this IP Core is the possibility to save MCU time wasted for handling HDLC/SDLC features, like bit stuffing, address recognition and CRC computation. To enable even more productivity, the DHDLC has an implemented FIFO buffer, for both receiver and transmitter. The DHDLC IP Core is fully synchronous with one clock domain design. All parameters are configurable by CPU, but there is also an another option. One can set all the parameters by modification constants in a source file. Thanks to it, there’s no need to waste silicon resources for unused features and constant settings.

The DHLC also features programmable number of bits for idle detection, byte alignment error detection and collision detect. Further to this, the DHLC also comes with NRZI coding support, RC-16 and CRC-32 computation and checking, address recognition for receiver and address insertion for transmitter, pad fill with flags option and transmitter clock generation.