Accelerator platform connects FPGA to POWER8 CPU

The reconfigurable hardware accelerator features shared virtual memory between the FPGA and processor which significantly improves system performance, efficiency and flexibility in high-performance computing (HPC) and data centre applications. Altera and IBM are presenting several POWER8 systems that are coherently accelerated using FPGAs at SuperComputing 2014.

The Altera and IBM combination are developing highly flexible heterogeneous compute solutions that bring new levels of performance and efficiency to POWER8 systems.

FPGA-accelerated POWER8 systems are optimised to enable compute- and processing-intensive tasks required in next-generation HPC and data centre applications, including data compression, encryption, image processing and search. Using CAPI to coherently attach FPGA accelerators to the fabric of a POWER8 processor and main system memory make the FPGA appear as simply another core on the POWER8 processor.

This results in shortened development time by greatly reducing lines of software code and reduced processor cycles versus conventional IO attached accelerators. A single FPGA-accelerated POWER8 server is able to operate at industry-leading levels of efficiency, allowing system architects to cut their data centre footprint in half.

“As today’s high performance computing applications evolve with rapidly changing workloads, it is imperative we build in flexible accelerators to make IBM POWER processors more efficient in IBM Power Systems and all OpenPOWER compatible systems,” said Brad McCredie, vice president of IBM Power development and OpenPOWER president. “The work Altera has done to provide FPGA-based reconfigurable hardware acceleration to our POWER processors enabled through CAPI allows software developers to build highly efficient, highly flexible, performance optimized systems.”

Altera and IBM have worked with board partner Nallatech to develop an OpenPOWER CAPI Development Kit for POWER8 that features Nallatech’s FPGA-based 385 card, the industry’s first CAPI FPGA accelerator card. This off-the-shelf development platform allows designers to start developing with CAPI in a POWER8 system.

The Altera SDK for OpenCL provides developers the resources they need to develop their own custom FPGA-based accelerators and gain a time to market, power and performance advantage. The release of the OpenCL 2.0 specification supports shared virtual memory capabilities which enable programmers to address memory shared by the host and accelerator using CAPI.

“Our work with the OpenPOWER Foundation has enabled us to deliver highly flexible heterogeneous compute platforms that target Power-based systems,” said David Gamba, senior director of the computer and storage business unit at Altera. “Altera is at the forefront of supplying Power users reconfigurable hardware accelerators based on CAPI that are supported with an OpenCL programming model. The result is highly optimised accelerators that deliver optimal FLOPs/Watt/dollar.”