Acceleration stack delivers 2-6x compute efficiency

According to the company, it provides the fastest path to realise 40x better compute efficiency with Xilinx FPGAs compared to x86 server CPUs and up to six times the compute efficiency over competitive FPGAs. Using dynamic reconfiguration, Xilinx enables silicon optimisation for the broadest set of performance-demanding workloads including machine learning, data analytics, and video transcoding. These workload optimisations can be done in milliseconds by swapping in the most optimal design bitstream.

Today Xilinx FPGAs enable hyperscale data centres to achieve 2-6x the compute efficiency in machine learning inference because DSP architectural advantages for limited precision data types, superior on-chip memory resources, and greater than one year technology lead over FPGA competition.

The Xilinx Reconfigurable Acceleration Stack includes math libraries designed for cloud computing workloads, application libraries integrated with major frameworks, such as Caffe for machine learning, a PCIe-based development board and reference design for high density servers, and an OpenStack support package making Xilinx FPGA-based accelerators easy to provision and manage.

“Flexibility and feature velocity – the ability to add new features rapidly through software – are important for hyperscale’s complex and constantly changing application landscape,” said Karl Freund, Senior Analyst, Machine Learning, for Moor Insights and Strategy. “The capability to reconfigure and optimise the accelerator as algorithms evolve – as Xilinx claims – is a compelling advantage in hyperscale environments.”

“The stack accelerates mainstream adoption of our FPGAs in hyperscale data centers,” said Nazeem Noordeen, Corporate Vice President, IP Solutions at Xilinx. “It delivers the fastest path to realise 2-6x the compute efficiency over FPGA competition.”