Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

With full production support for all Xilinx(R) Virtex(R)-6 and Spartan(R)-6 FPGA families, the ISE 12 release continues its evolution as the industry's only domain-specific design suite with interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded processing, and system-level design. In addition, Xilinx incorporated a number of software infrastructure and methodology enhancements that improve run time, streamline system integration, and expand IP interoperability across its latest generation device families and Targeted Design Platforms.

Xilinx FPGAs are the innovation platform for tens of thousands of designers across a wide range of applications and markets. Designers continue to adopt our FPGAs for their next generation products, because they can balance the demands for reduced power and high performance with lower system costs, said Tom Feist, senior marketing director for ISE Design Suite at Xilinx. ISE 12 design suite is optimized for these goals with power and cost-saving software innovations that maximize the capabilities of Virtex-6 and Spartan-6 devices and platforms and increase overall design productivity.

Intelligent Automation for Power Optimization

ISE Design Suite 12 introduces the FPGA industry's first intelligent clock-gating technology with fully automated analysis and fine-grain (logic slice) optimization capabilities specifically developed to reduce the number of transitions, a primary contributing factor of dynamic power dissipation in digital designs. The technology works by analyzing designs using a series of unique algorithms to detect sequential elements ('transitions') within each FPGA logic slice that do not change downstream logic and interconnect when toggled. The software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network.

Greater Productivity, Better Performance

Advanced design preservation capabilities in the ISE 12 design suite enable designers to reach design closure fast with repeatable timing results. Designers can partition designs to focus on achieving required timing for critical blocks, and lock those blocks to preserve placement and routing while they work on the rest of the design. To foster plug-and-play FPGA design, Xilinx is standardizing IP interfaces on the open ABMA(R) 4 AXI(TM)4 interconnect protocol, which eases integration of IP from Xilinx and third party providers and maximizes system performance. Xilinx also worked with ARM to define the AXI4, AXI4-Lite, and AXI4-Stream specifications for efficient mapping into its FPGA architectures.

Partial Reconfiguration Lowers Cost

Partial reconfiguration is great for space applications. Not only does it make on-orbit 'upgrades' possible, but it also drastically reduces the rad-hard, non-volatile memory requirement, which is expensive and not very dense, said Jonathon Donaldson, an embedded systems engineer at Sandia National Laboratories. We've been using partial reconfiguration technologies since their inception with Xilinx FPGAs, and are pleased with the quality progression of the tools. The tools have reached the point where they are practical to use in almost any case, and are now even easier with the newest version of the ISE Design Suite.

Partial reconfiguration technology allows the dynamic modification of FPGA logic blocks by downloading partial bit files without interrupting the operation of the remaining logic. ISE Design Suite 12 makes this technology easy to use with Xilinx FPGAs by providing an intuitive interface and simplified methodology that closely aligns with the standard ISE design flow with which users are familiar. The ISE partial reconfiguration flow now uses the same proven Xilinx tools and techniques for timing closure, design management and floorplanning, and design preservation.

Support for fourth generation 'on-the-fly' partial reconfiguration technology enables designers to dramatically reduce system cost and power consumption by fitting sophisticated applications into the smallest possible device. Developers of next-generation wired Optical Transport Network (OTN) solutions can implement a 40G multi-port muxponder interface with one-third fewer resources as compared to devices without partial reconfiguration (see March 16, 2010 news release). Many other applications including software-defined radio also benefit from the increased flexibility provided by on-demand reconfiguration with Xilinx FPGAs.

Start Designing Today

ISE Design Suite 12 innovations will rollout in phases with intelligent clock gating for Virtex-6 FPGA designs shipping now with the 12.1 release, partial reconfiguration for Virtex-6 FPGA designs starting in the 12.2 release, and AXI4 IP support to follow in the 12.3 release. The ISE 12 suite works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics, and Synopsys.

Additionally, the 12.1 software features an average of 2X faster logic synthesis and 1.3X faster implementation run times for large designs than previous versions and an improved embedded design methodology. It also includes an expanded offering of production qualified IP for the Virtex-6 FPGA Multi-mode Radio Targeted Design Platform, Spartan-6 FPGA Industrial Automation and Industrial Imaging Targeted Design Platforms, as well as the Virtex-6 HXT FPGA 100G OTN and Packet Processing Targeted Design Platform that will be available later this year.