Workflow for 3D full-wave chip package board modelling

10th June 2015

Nat Bowers

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Computer Simulation Technology has demonstrated an innovative workflow that combines the full wave simulation and extraction capabilities of CST STUDIO SUITE with the accuracy of Synopsys HSPICE at booth #2827 during DAC 2015. Engineers concerned with the design of modern electronic systems can take advantage of this new workflow.

The workflow enables the combination of an industry-standard circuit simulator, HSPICE, with the accurate full-wave extraction of 3D components and interconnects performed by CST STUDIO SUITE.

In the centre of this workflow is CST DESIGN STUDIO, the block schematic tool at the heart of CST STUDIO SUITE. In chip-package-board co-design, an engineer can model a full channel system by linking blocks together. These blocks can represent circuits, IBIS models, 3D elements such as connectors, flip-chip or BGA, and arbitrary HSPICE models using CST STUDIO SUITE version 2015.

All these blocks can then be simulated together as a system. The 3D electromagnetic full-wave solvers in CST STUDIO SUITE can perform the extraction of the channel and create a new, simulation-ready HSPICE netlist representing the full channel which can be passed on to HSPICE for simulation and analysis, automatically.

Dr. Leonardo Sassi, Product Planning Manager, EDA and interoperability, CST, comments: “Accuracy is essential in high speed system design, and engineers are increasingly demanding integrated solutions. Through our link to Synopsys HSPICE, we now provide a straightforward system workflow incorporating 3D electromagnetic simulation to meet this challenge!”

The automated link to Synopsys HSPICE is available with CST STUDIO SUITE 2015 SP 3.