WaveFormer Lite Generates Mixed Signal HDL Test Benches for all FPGA design flows

WaveFormer Lite Generates Mixed Signal HDL Test Benches for all FPGA design flows SynaptiCAD has just released a major upgrade to WaveFormer Lite, it's entry level tool for generating VHDL and Verilog test benches graphically from timing diagrams drawn by the user. Previously only available as part of the Actel Libero package, WaveFormer Lite can now be purchased directly from SynaptiCAD. WaveFormer Lite generates native VHDL and Verilog testbench code, so it's compatible with all FPGA/ASIC vendors and tool flows without requiring any special runtime engines.