Xilinx Vivado Design Suite Accelerates Time to Integration and System-Level Design to Stay a Generation Ahead

Accelerated Time to IP Creation and Integration

To accelerate the creation of highly integrated, complex designs in All Programmable FPGA devices, Xilinx has delivered the early access release of the Vivado IP Integrator (IPI). Vivado IPI accelerates the integration of RTL, Xilinx IP, third party IP and C/C++ synthesized IP. Based on industry standards such as the ARM AXI interconnect and IP-XACT metadata for IP packaging, Vivado IPI delivers intelligent correct-by-construction assembly of designs co-optimized with Xilinx All Programmable solutions. Built on the foundation of the Vivado Design Suite, IP Integrator is a device and platform aware interactive, graphical and scriptable environment that supports IP-aware automated AXI interconnect, one-click IP subsystem generation, real-time DRC, interface change propagation, and a powerful debug capability. When targeting a Zynq-7000 All Programmable SoC, embedded design teams can now more rapidly identify, reuse, and integrate both software and hardware IP targeted for the dual-core ARM processing system and high performance FPGA fabric.

Vivado has already provided us with a major leap in our productivity for development of reconfigurable computing platforms and applications, said Shep Siegel, CTO of Atomic Rules LLC. The combination of Vivado IPI and 7 series silicon is enabling us to accelerate our development schedules. We are impressed with the innovation that Xilinx is delivering both in silicon and design flows to address our end customer requirements.

Libraries for Accelerated System-Level Design

To accelerate C/C++ system level design and high-level synthesis (HLS), Xilinx has enhanced its Vivado HLS libraries with support for industry standard floating point math.h operations and real-time video processing functions. Over 350 active users and 1000+ customers evaluating Vivado HLS will now have immediate access to video processing functions integrated into an OpenCV environment for embedded vision running on the dual-core ARM processing system. The resulting solution enables up to a 100X performance improvement of existing C/C++ algorithms through hardware acceleration. At the same time, Vivado HLS accelerates system verification and implementation times by up to a 100X compared to RTL design entry flows. When targeting a Zynq-7000 All Programmable SoC, design teams can now more rapidly develop C/C++ code for the dual-core ARM processing system, while compute intensive functions are automatically accelerated in the high performance FPGA fabric.