Verification IP supports popular 3D memory standards

28th October 2014

Barney Scott

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Cadence's Verification IP (VIP) supports all popular 3D memory standards, including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP allows designers to accelerate the verification of memory interfaces and achieve earlier SoC verification closure for compute server applications, mobile devices, high-performance graphics and network applications.

The VIP models feature direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.

All leading third party simulators, verification languages and methodologies are supported by the model. This enables SoC verification teams to verify the correctness of interfaces to these specialised memories, using their chosen method.

Robert Feurle, Vice President, Compute and Networking Marketing, Micron, said: “Memory is a critical factor in increasing functionality and performance of advanced system topologies. The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as HMC.”

"3D memories are increasingly becoming essential to the next gen of electronic products," added Erik Panu, Vice President, Research & Development, IP Group, Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."