Design
Cadence Releases Verification IP For USB SuperSpeed Inter-Chip Specification
Cadence Design Systems has today announced production-proven verification IP for the new USB SuperSpeed Inter-Chip specification, enabling customers to thoroughly verify designs deploying the latest extension of the USB 3.0 protocol. The SSIC specification combines the MIPI Alliance physical interface with the upper layers of the USB protocol to enable USB 3.0 to connect chips within a mobile device.
ThisCadence USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol, said James Cheng, senior vice president, Global Unichip. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage.
The SSIC extension of the USB 3.0 protocol is an important new tool for developers of mobile, smartphone and tablet devices because it offers higher data rates and power efficiency for internal use, said Martin Lund, senior vice president, research and development, SoC Realization Group. Our USB 3.0 VIP has been used to verify over 100 designs, and we incorporated the knowledge gained to create this new product for engineers seeking the benefits of using the SSIC extension.
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