USB 3.0 host IP offers 40% lower dynamic power consumption

Cadence offers a complete USB 3.0 solution including the controller, PHY and verification IP. The certified USB 3.0 host solution for 16FF+ features an innovative architecture developed by FinFET design experts within Cadence and offers a 40% reduction in dynamic power consumption versus previous generations of the IP on other process nodes. To achieve this power reduction, the integrated USB host xHCI controller and PHY IP utilise power and clock gating in order to conserve energy as the USB protocol goes into a low-power sub-state.

Additionally, the PHY is optimised to ease integration. With a reduced pinout, there are fewer combinations to verify and less complexity with fewer complex software interactions that need to be tested and debugged.

“For our mobile and consumer customers, achieving USB 3.0 host certification on 16FF+ is critical because it signifies a reliable and low-risk path toward successful, advanced-node SoC design,” said Osman Javed, Product Marketing Director, Cadence. “The complete solution of controller, PHY and verification IP enables customers to significantly reduce integration time and get their products to market faster. Our IP solution is available in a wide range of configurations that meets the needs of our customers looking to design for both high-performance and embedded, low-power applications.”

“As a long-term member of USB Implementers Forum, Cadence delivers USB design and verification IP that reduces the integration and verification effort for today’s complex SoCs,” said Jeff Ravencraft, President and COO, USB-IF. “USB-IF certification of IP on TSMC 16FF+ is a critical step to provide the industry with proven solutions to build interoperable, reliable USB products for consumers.”