Updated Lattice Diamond Fpga Design Software Supports New MachXO2 PLD Family

“We have had an extremely positive response from existing and new customers to the Lattice Diamond design environment, which was released in June. The design exploration capability and improved user productivity enabled by Lattice Diamond 1.1 software are now available to users of our new MachXO2 PLD family,” said Mike Kendrick, Lattice’s Manager of Software Product Planning. “Design exploration targeting low power and cost sensitive applications is further broadened for the MachXO2 PLD user with a choice of synthesis tools.”

Support for the New MachXO2 PLD Family
Lattice Diamond 1.1 software includes support for the entire MachXO2 PLD family, also announced today. The Lattice Diamond design environment enables users to easily explore design alternatives as they target cost sensitive, low power, high volume applications – the type of application ideally suited for the MachXO2 family.

Initial Support for Lattice Synthesis Engine
The Lattice Diamond 1.1 design environment includes the initial customer beta release of the Lattice Synthesis Engine (LSE). LSE is the result of several years of development, initially focused on internal Lattice FPGA architecture development and now made available to Lattice users. With support initially for the MachXO2 and MachXO PLD families, LSE gives those users an additional choice of synthesis tool for design exploration. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond 1.1 design environment as a synthesis tool choice.

Updated Support for the LatticeECP3 FPGA Family
This release supports the final production power, timing and SSO analysis values for the entire LatticeECP3 FPGA family, including the recently released ECP3-17EA device. Notably, ongoing improvements to the synthesis, MAP and PAR implementation engines have resulted in an average FMax improvement of 20% on larger designs, such as those targeted to the ECP3-150EA device. Enhancements to the targeting of behavioral HDL to the sysDSP™ block’s cascading feature have resulted in improved performance, specifically a 30% performance improvement for the Lattice FIR IP
.
Design Flow Enhancements
Lattice Diamond 1.0 incorporated an intuitive, modern GUI that enabled several new concepts that help users quickly explore design alternatives to meet their cost, power and performance goals. The Lattice Diamond 1.1 release further builds on this approach, with several design flow enhancements that include even faster recalculation of static timing analysis in the Timing Analysis View.

Additional Simulation Features for All Lattice Diamond Users
All Lattice Diamond free software users now have the ability to simulate mixed language designs and access to more simulator capacity to handle even larger designs. Previously this capability was available only to users that purchased the Lattice Diamond subscription license.

Third Party Tool Support
Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition II simulator is included for Windows.
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.

Pricing and Availability