UltraSoC updates advanced semiconductor IP & software tool

As the cost of developing complex SoCs continues to rise, and the business risks from schedule slippage become larger, the industry has realised that better tools for debug, verification and optimisation are critical. The advent of emulation and prototyping platforms has eased pre-silicon tasks, but post-silicon verification and optimisation remains a major challenge for the industry. UltraSoc addresses this challenge. Many of the new capabilities and features are in software and tools – particularly in interfacing and supporting standard development environments. Specifically:

• Richer support for analytics and visualisation, leading to the use of big data techniques for debugging and development;
• New tools and analysis capabilities to assist in performance monitoring and system optimisation;
• Enhanced support for developers using Python scripts to interact with UltraSoC IP for post-processing, analytics and visualisation;
• Migration to Eclipse version 4.5 (“Mars”) with all the capabilities that come from an industry standard IDE;
• Support for the GDB industry standard open-source debugger;
• Direct integration with Lauterbach’s industry standard TRACE32 development environment; and
• Direct integration with the new version of CEVA’s toolchain for CEVA DSP.

New hardware and semiconductor IP capabilities include:

• Enhanced processor analytic modules to interface to MIPS and CEVA cores for debugging, trace and run-control. These complement the existing ARM and Xtensa core support;
• Capability to support other cores, including the open-source RISC V core;
• Support for ECC, parity and check sum logic, important for high-reliability systems. This is a key part of UltraSoC’s capabilities to support functional safety, automotive and ISO26262; and
• General availability of the new Universal Streaming Communicator (USC) that enables a variety of interface and communication systems to the SoC, including serial wire debug style communication and a high speed SerDes interface.

Rupert Baines, CEO, UltraSoC, commented: “UltraSoC is committed to an aggressive program of continuous development for our products. Our technology helps SoC developers to understand how their chip really operates post-silicon: simplifying software development, accelerating time-to-market, fixing bugs and optimising performance. The new capabilities we are announcing today, engineered in response to extensive customer feedback and experience in the field, represent another step forward in the paradigm shift we are enabling in SoC design; improved analytics and visualisation; addressing a far wider range of hardware applications; and giving SoC teams complete freedom in their choice of development flow and tools.”

UltraSoC’s suite of silicon IP allows designers to create an on-chip infrastructure that non-intrusively monitors the digital aspects of the chip’s behaviour – both hardware and software. The engineering team can gain a much more intimate understanding of the often complex interactions between diverse on-chip processor blocks, custom logic and system software. These capabilities are valuable both in development and in-field, when they can be used to spot unexpected behaviour caused by bugs or by malicious interference and to analyse performance trends.