UltraSoC & Cadence deliver universal debug for multicore SoCs

Xtensa technology enables the system architect to create power-efficient, high-performance processors and DSPs customised to the exact needs of their design. This, in turn, allows the creation of SoCs in which key tasks are offloaded from the host processor to multiple heterogeneous Xtensa processors, delivering outstanding overall performance and power consumption figures.

UltraDebug is designed to speed pre- and post-silicon debugging in exactly these environments, allowing the designer to ‘bake in’ an on-chip debug infrastructure that is tailored to the specific requirements of their system design. It enables holistic debugging of system software running on chips that incorporate multiple, heterogeneous functional units, as well as custom logic designed in-house.

Xtensa processors are the latest CPU family to be supported within UltraDebug, which already includes direct support for other common processor cores.

"UltraSoC has innovative technology when it comes to SoC debug," said Chris Jones, Product Marketing Group Director of the Tensilica division of the IP Group at Cadence. "Their technology helps designers to create competitive products quickly and we're looking forward to working together to solve the SoC debug challenge, which we believe is one of the challenges facing the semiconductor industry today."

Rupert Baines, CEO, UltraSoC, commented: "Xtensa processors are a proven route to efficient, high-performance SoCs. Today's application processors are not optimised to handle the vast range of tasks required in today's advanced consumer products, in particular datapath processing. Xtensa technology provides a solution to that problem, offloading tasks from the host processor and creating highly optimised multicore SoCs. We're very much in tune with this vision of the SoC, and delighted to be working with an industry-leader like Cadence to make it happen."