THE COLD HARD FACTS ABOUT LOW POWER PROGRAMMABLE LOGIC

QuickLogic contracted a third party to study the design issues around low power FPGA and CPLD technology, and author a white paper describing different architectures. The white paper presents actual board-level test data comparing each vendor's 'low power' programmable logic, including details on why and when different architectures will consume excessive amounts of power. The data includes in-rush current at device start-up together with static, dynamic and idle-mode power consumptions during normal operation.

The demo platform video clip and the power consumption white paper are available at no cost and can be downloaded from .

The demo platform can also be viewed at the Consumer Electronics Show (CES) in Las Vegas from January 8 to January 11 at the QuickLogic Demo Suite at the Circus Circus Hotel. To register please go to http://www.quicklogic.com/cesdemo/

The need to quickly and easily integrate more functionality within ever-decreasing board space, power budgets and market windows drives designers of portable electronics towards using flexible, low power programmable logic solutions, said Brian Faith, QuickLogic's Senior Director of Marketing. However, selecting the right programmable logic isn't easy and low power claims are often that - just claims. With our Low Power Programmable Logic Comparison Package, we've taken the guesswork out of comparing devices so designers can focus on design and not on creating comparison metrics, or trying to sort through oft-times confusing data sheets.