Testing 3D stacked memories

Through-silicon vias (TSVs) result in shorter and thinner connections that can be distributed across the die. TSVs reduce package size and power consumption, while increasing performance due to the improved physical characteristics of the very small TSV connections compared to the much larger bond wires used in traditional packaging. Applications involving the stacking of one or more memory die on top of a logic die, for example using the JEDEC Wide IO standard bus interface, are ramping quickly.
One key challenge is how to test the TSV connections between the stacked memory and logic die. There is generally no external access to TSVs, making the use of automatic test equipment difficult if not impossible. Functional test (for example, where an embedded processor is used to apply functional patterns to the memory bus) is possible but is also slow, lacks test coverage and offers little to no diagnostics. Therefore, ensuring that 3D ICs can be economically produced calls for new test approaches.

A new embedded test method that works for test and diagnostics of memory on logic TSVs is built on the built-in self-test (BIST) approach that is already commonly used to test embedded memories within SoCs. For 3D test, a BIST engine is integrated into the logic die and communicates to the TSV-based memory bus that connects the logic die to the memory, as illustrated in Figure 1.
For this solution to work, a number of critical advances over existing embedded memory BIST solutions were necessary.

One of these advances is an architecture that allows the BIST engine to communicate to a memory bus rather than directly to individual memories. This is necessary partly because multiple memories may be stacked within the 3D IC, but mostly to allow the BIST engine to test the memory bus itself, and hence the TSV connections, rather than just the memories. Test algorithms tailored to cover bus-related failures are used to ensure maximum coverage and minimal test time. Because of this directed testing of the memory bus, the 3D BIST engine can also report the location of failures within the bus, which allows diagnosis of TSV defects.

##IMAGE_2_C##
Figure 1: 3D BIST for Memory to Logic TSV testing

The architecture used to test bussed external memories is shown in Figure 2. In this approach, the BIST engine is placed behind the functional memory interface and shares this interface with the functional control logic. All BIST transactions with the memories are communicated through the interface. The functional interface takes care of handling all signal synchronisation between the BIST engine and the memories. This includes for example managing the data transfer rate difference between the BIST engine and DDR memories.

Although the majority of embedded memories are SRAMs, stand-alone memory die used in 3D stacked applications are generally DRAMs (usually following the JEDEC Wide IO interface standard). As a result, it is important that the 3D memory BIST engine have the ability to interface and properly test DRAM memories.

More specifically, the BIST engine supports typical DRAM read/write protocols, addressing protocols such as bursting, and memory refresh operations.

Another critical advance in this new 3D BIST solution is that it is run-time programmable. Using only the standard IEEE 1149.1 JTAG test interface, the BIST engine can be programmed in silicon for different memory counts, types, and sizes. Because the BIST engine is embedded into the logic die and can’t be physically modified without a design re-spin, this adaptability is essential. With full programmability, no re-design is needed over time even as the logic die is stacked with different memories and memory configurations for different applications. For greater efficiency and ease-of-use, the BIST engine supports a mix of both hard-coded settings and run-time programmability. The engine is provided with a number of pre-determined memory support configurations so that in most cases, no programming is needed during manufacturing or system level testing. The run-time programmability is only used in those situations where the memory support requirements were not anticipated.

##IMAGE_3_C##
Figure 2: Architecture for testing bussed external memories.

An automated flow is available for programming the BIST engine (for wafer or final package testing) to apply different memory test algorithms, to use different memory read/write protocols, and to test different memory bus widths and memory address ranges. The patterns needed to program the engine through the JTAG interface pins are generated in common formats, such as WGL or STIL, to be loaded and applied by standard automatic test equipment.

Because this 3D test solution is embedded, it needs to have minimal impact on design flows and schedules and no impact on design performance. This is done through an automated RTL flow that integrates the BIST engine into the logic die and fully verifies its operation. The flow is compatible with all standard silicon design flows and methodologies. There is no impact to design performance because the BIST engine intercepts the memory bus with multiplexing logic placed at a point in the functional path with sufficient slack.

This new embedded solution for testing TSVs between memory and logic die is cost effective, giving the best balance between test time and test quality. Engineers considering designing in 3D need to feel confident that they can test the TSVs without excessive delay or risk. This solution shows how that can be achieved and opens the way for a more rapid adoption of 3D design techniques.
The approach described above forms part of the functionality of the Mentor Graphics Tessent MemoryBIST product. A 3D test white paper is available to download below.

Author profile: Stephen Pateras is product marketing director for Mentor Graphics Silicon Test products. He was previously the VP of Marketing at LogicVision. While at LogicVision Stephen also held senior management positions in engineering, and was instrumental in defining and bringing to market several generations of LogicVision’s semiconductor test products. From 1991 to 1995, Stephen held various engineering lead and management positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.