Design
Teklatech’s floorplanning EDA tool exclusively selected by Think Silicon
Teklatech, a technology leader in floorplanning and clock distribution network solutions, has announced that its FloorDirector product has been exclusively chosen by Think Silicon for use in 90 nm and 65 nm designs. Think Silicon, an innovative European design center and supplier of various IP and turnkey solutions, has selected the FloorDirector EDA tool for its unique floorplanning optimization technology which is required for a wide range of SoC applications, including multimedia, DSP, wireless, networking and mobile. FloorDirector’s ability to deliver SoC power shaping and provide robustness to on-chip-variation were key factors in Think Silicon’s decision.
“U“We were impressed by FloorDirector's ability to accurately analyze power signatures”, said Iakovos Stamoulis, Director of Technology for Think Silicon. Because of FloorDirector’s IR drop aware floorplanning, we were able to meet timing and power requirements easily and improve our time-to-market.”
The FloorDirector floorplanning engine analyzes the dynamic power signature of every system block and identifies initiators of critical voltage drop chains in the design. Utilizing novel power shaping techniques and statistical clock timing analysis, FloorDirector provides system-level IR drop and noise reduction solutions while maintaining scalable clock-level synchronization. This allows engineers to floorplan a chip for optimal power peak flattening, leading to reduced dynamic IR drop and improving overall signal and power integrity.
Sharon Akler, Director of Technical Marketing at Teklatech noted: “Without doubt, FloorDirector’s ability to reduce dynamic IR drop, improve noise margins, and above all establish a predictable path to production, perfectly matches the requirements of the state-of-the-art System on Chip (SoC) market. This collaboration with Think Silicon clearly demonstrates how semiconductor companies can leverage our technology in a broad range of applications, including digital and mixed signal ICs.”