Synthesis engine addresses RTL productivity challenges

The Genus synthesis solution incorporates a multi-level massively parallel architecture that delivers up to five times faster synthesis turnaround times and scales linearly beyond 10m instances. In addition, the tool’s physically aware context-generation capability can reduce iterations between unit- and chip-level synthesis by two times or more. This powerful combination enables up to ten times improvement in RTL design productivity.

The tool performs timing-driven distributed synthesis of a design across multiple cores and machines. All key steps in the synthesis flow leverage both multiple machines and multiple CPU cores per machine. The complete timing and physical context for any subset of a design can be extracted and used to drive RTL unit-level synthesis with full consideration of chip-level timing and placement, significantly reducing iterations between chip-level and unit-level synthesis runs.

The Genus synthesis solution and the Cadence Innovus implementation system, a next-gen physical implementation solution, share an enhanced four times faster timing-driven global router that enables tight correlation of both timing and wirelength to within 5% from synthesis to place and route. The solution incorporates a new datapath optimisation engine that concurrently considers many different datapath architectures across the whole design and then leverages an analytical solver to pick the architectures that achieve the globally optimal PPA. This engine delivers up to 20% reduction in datapath area without any impact on performance.

“Processors for automotive and industrial markets are driving higher-levels of integration and complexity. This requires larger design partitions to deliver the efficiencies and time-to-market demanded by our customers,” said Anthony Hill, Director of Processor Technology, Texas Instruments. “The highly-scalable Genus synthesis solution from Cadence has enabled more than a five times improvement in turnaround time, enabling us to realise production-quality timing-driven synthesis of up to three-million instance partitions in less than eight hours.”

“With Genus synthesis solution, we see a significant opportunity to improve RTL design productivity and make more aggressive architecture-level optimisations to improve PPA,” commented Dr. Anirudh Devgan, Senior Vice President and General Manager, Digital & Signoff Group, Cadence. “Early customers are already deploying the solution in their RTL design flows and reporting significantly better turnaround times and throughput compared to competing solutions.”